Install guide

ARMY TM 5-6675-308-34
MARINE CORPS TM 08837A-34/2
by no. 3 control circuit card assembly, and has priority
over normal instruction execution.
1. Memory input. To store information in
the memory unit, the request ing device generates a
memory initiation request and the memory address
input. The initiation request is sent to the CPU where
the CPU control logic determines access to the data
bus. When the request is accepted, the data to be stored
in memory is loaded on the SDB and stored in the
addressed memory location.
2. Memory output.
To read information
from the memory unit, the requesting device generates
an initiation request and a memory address input in the
same manner as for memory input transfer. When the
request is accepted, the data from the addressed mem-
ory location is loaded on the SDB and sent to the
requesting device.
(g) Interrupt control
The interrupt control
logic mechanizes three separately addressable indepen-
dent hardware interrupt functions. Three interrupt dis-
cretes, priority interrupt, service interrupt, and internal
interrupt, cause the next instruction to be taken from
specifically related RAM address locations containing
previously stored 16-bit addresses. The internal inter-
rupt aids the CPU to diagnose and interrupt operation
in the event of an arithmetic overflow or divide fault.
The service interrupt is normally associated with an
external device. The priority interrupt may be associ-
ated with a power (failure) condition. For more infor-
mation on the interrupts, refer to the 1/0 section
description.
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