Install guide

ARMY TM 5-6675-308-34
MARINE CORPS TM 08837A-34/2
1. The program counter, one of the RAM
registers, is a 16-bit register that holds the next instruc-
tion to be accessed into memory. As each instruction is
executed, the program counter contents are incre-
mented by one, thus providing the address of the next
instruction. The program counter is also used as a
reference register for addressing operands into memory.
2. The seven 16-bit index registers, also
RAM registers, are generally used as reference registers
for memory address operations.
3. The RAM 16-bit extension accumulator is
an extension of the accumulator. During instructions
where the operand is 32 bits in length, the extension
accumulator register is linked with the accumulator to
provide a 32-bit accumulator. The extension accumula-
tor always contains the 16 least significant bits of data
in double-precision operations.
4. The RAM 16-bit quotient register is used
to hold the quotient (result) when the CPU executes a
divide operation.
5. The RAM 16-bit base register is used
primarily as a reference register for loading and storing
the index registers.
6. Three RAM addresses are provided for
interrupts. These include external service requests (ser-
vice interrupt address), internal error (internal interrupt
address), and power failure or program trace operations
(priority interrupt address). The contents of these three
addresses can be modified.
(c) Memory register. The 16-bit memory regis-
ter is used to receive information from memory via the
SDB for execution during a CPU operation. The infor-
mation may be either a command or an operand.
(d)
Adder unit. The function of the adder unit is
to operate logically on data under control of a CPU
instruction and to generate a result. The computation
occurring in the adder unit results in an address modi-
fication or an execution of the instruction.
(e)
A-switch. The A-switch controls flow of data
into the adder unit from either the accumulator or the
random access memory.
(f) B-switch. The B-switch controls data flow
into the adder unit from the memory register, status
register, and arithmetic counter.
(g) Output switch. The output switch feeds the
adder unit output onto the data bus for memory ad-
dressing, data storage, or input/output device commu-
nication.
(h) Holding register. The 16-bit holding register
temporarily holds the adder unit outputs that are des-
tined for random access memory storage.
(2) Control section. The control section decodes
instructions and generates the necessary microcom-
mands and timing to control data flow through the data
section. The control section is contained on no. 1, no, 2,
and no. 3 control circuit card assemblies and consists of
the following major elements:
Instruction register
Control logic
Status register
Arithmetic counter
Clock generator
Direct memory access (DMA) controls
Bus and switch controls
(a) Instruction register. The 16-bit instruction
register no. 1 control circuit card assembly receives the
instruction accessed from memory via the data bus. The
output from the instruction register is routed to the
RAM controls and includes the instruction decode logic.
The RAM controls are used to address a RAM register
in accordance with the decoded instructions. The out-
put from the instruction decode logic is used to control
the balance of the CPU.
(b) Control logic. The control logic consists of
the state counter and state control logic. The state
counter, located on no. 3 control circuit card assembly,
is used primarily for execution of all CPU instructions.
As each state is entered, controls are set to enable
portions of the instruction cycle to occur. The state
counter is controlled by the decode of the instruction to
be executed. Additional means for instruction execution
are provided by the state control logic. The logic and
circuitry are located on no. 2 control circuit card
assembly.
(c) Status register. The 8-bit status register on
no. 3 control circuit card assembly contains three indi-
cator bits and three interrupt bits. The remaining two
bits are not used. The results of arithmetic computa-
tions are used to set the condition indicators on the
status register. The occurrence of interrupts causes the
interrupt bits to be set. Output from the status register
is routed to the output switch.
(d) Arithmetic counter. The arithmetic counter
located on no. 3 control circuit card assembly, is used
during execution of multioperation instructions such as
multiply, divide, shift and normalize operations.
(e) Clock generator. The CPU operates with
synchronous control from a 4-MHz clock signal gener-
ated on no. 3 control circuit card assembly,
(f) Direct memory access control Direct mem-
ory access (DMA) occurs when the CPU, I/O Section or
a test device needs to store data into memory or read
data from memory. The DMA operation is controlled
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