Install guide

ARMY TM 5-6675-308-34
MARINE CORPS TM 08837A-34/2
reads the keyboard word, the parity status flip-flops are
reset. A long loop serial bus self-test function is pro-
vided in the CDU by wrapping around bits 8 through
15 of the address word as bits 8 thru 15 of the keyboard
word. There is no restriction on the bit patterns used on
these bits.
(b) The second type of CDU word provides an
additional self-test feature for the CDU. This allows the
computer to read the contents of any of the eight
display registers without destroying the contents of the
register or affecting the appearance of the display. To
read a register, the same sequence as reading the key-
board word is followed except that the self-test bit 4 is
(on) and the subaddress code bits 5 thru 7 must be used
to identify the display register contents desired by the
computer.
b. Display Logic Registers and Drivers. Eight 16-
bit data registers are movided for the storage of display
data. Each of these registers can be loaded or read by
the computer as described in paragraph a. Data con-
tained in these registers control the various front panel
displays, electroluminescent lighting control relay, and
audible alarm. Lamp drivers and keep-warm resistors
are employed to minimize lamp current surges.
c. Keyboard and Associated Logic. The CDU em-
ploys a keyboard consisting of a row-column switch
matrix. Scanning logic sequentially examines the status
of each key and stops scanning when a key is pressed.
The resultant key code (which corresponds to the
scanned address) is inserted into the keyboard word
transmitted from the CDU as described in paragraph a.
Since there is no register within the CDU to hold the
key code, the keyboard word must be requested by the
computer often enough to preclude the possibility of
missed keyboard actuations.
d. Discrete Logic. The CDU receives and transmits
the following discrete signals.
(1) Received discrete signals.
(a) Power reset, sets internal logic to initial
state.
(b) Bit flag set, sets CDU bit flag.
(c) Bit flag reset, resets CDU bit flag.
(d) Malfunction; computer, battery, charging,
and IMU malfunction discrete signals light respective
indicators,
(2) Transmitted discrete signals,
(a) ON/OFF controls power to the PADS.
(b) ENTER enables a power off sequence to the
PADS.
(c) CDU Power Requirements. The following
CDU power is received via the computer,
+ 5V ±2% logic power,
O to + 5.5V lamp power.
+ 24V ±20% at 120 ma maximum, fault indicator
power.
115 VAC ±l0%, 400 Hz ±5% at 60 ma maximum,
panel lighting.
2-4. Computer Functional Description. The computer
consists of three major functional sections; the central
processing unit (CPU) and memory, input/output (I/0)
section, and computer power supply. The computer is
functionally illustrated in figure FO-2. The CPU and
memory are the computational and storage element of
the computer. The 1/0 section provides interface be-
tween the CPU and memory unit, IMU, and CDU. A
16-bit bidirectional data bus provides a common path
for transferring instructions and operands from memory
to the CPU for processing. It also provides for transfer-
ring addresses and data generated by the CPU to the
memory. The bidirectional data bus also provides a
path for bidirectional data between the CPU and mem-
ory and the 1/0 section. A power supply, the third
major section, provides regulated power for the com-
puter. The following paragraphs describe each func-
tional section of the computer.
a. Central Processing Unit. The CPU consists of
two sections; the data section and the control section.
(1) Data section. The data section comprises the
arithmetic unit and its associated data registers. Both
addresses and data are generated in the data section.
The data section is contained on the 16-bit data circuit
card assembly and consists of the following major
elements:
Accumulator
Random access memory (RAM)
Memory register
Adder unit
A-switch
B-switch
Output switch
Holding register
(a) Accumulator. The 16-bit accumulator is the
main arithmetic register in the CPU. The results of
most arithmetic operations are held in the accumulator,
including any residual remainder after a divide opera-
tion.
(b) Random access memory. The RAM consists
of sixteen 16-bit registers. Since each RAM register has
a unique address, the contents of any register can be
accessed.
2-3