Specifications

Table Of Contents

Code for Third-Party Readers

36 SkyePlus™ MXH and MXU Multiplexer Reference Guide

/************************************************************

* Intermediate bit calculations

************************************************************/

//set dir registers for writing and write a 1 to control lines

#define MUX_A0_WRITE_HI {MUX_A0_DIR &= MUX_A0_DIR_MASK; MUX_A0_IO |= MUX_A0_IO_MASK;}

#define MUX_A1_WRITE_HI {MUX_A1_DIR &= MUX_A1_DIR_MASK; MUX_A1_IO |= MUX_A1_IO_MASK;}

#define MUX_A2_WRITE_HI {MUX_A2_DIR &= MUX_A2_DIR_MASK; MUX_A2_IO |= MUX_A2_IO_MASK;}

//set dir registers for writing and write a 0 to control lines

#define MUX_A0_WRITE_LO {MUX_A0_DIR &= MUX_A0_DIR_MASK; MUX_A0_IO &= ~MUX_A0_IO_MASK;}

#define MUX_A1_WRITE_LO {MUX_A1_DIR &= MUX_A1_DIR_MASK; MUX_A1_IO &= ~MUX_A1_IO_MASK;}

#define MUX_A2_WRITE_LO {MUX_A2_DIR &= MUX_A2_DIR_MASK; MUX_A2_IO &= ~MUX_A2_IO_MASK;}

//set dir registers for reading

#define MUX_A0_READ_ENBL (MUX_A0_DIR |= ~MUX_A0_DIR_MASK)

#define MUX_A1_READ_ENBL (MUX_A1_DIR |= ~MUX_A1_DIR_MASK)

#define MUX_A2_READ_ENBL (MUX_A2_DIR |= ~MUX_A2_DIR_MASK)

//read IO values and normalize

#define MUX_A0_READ_VAL ((MUX_A0_IO & MUX_A0_IO_MASK)/MUX_A0_IO_MASK)

#define MUX_A1_READ_VAL ((MUX_A1_IO & MUX_A1_IO_MASK)/MUX_A1_IO_MASK)

#define MUX_A2_READ_VAL ((MUX_A2_IO & MUX_A2_IO_MASK)/MUX_A2_IO_MASK)

/************************************************************

* Final values used for device detection and port addressing

************************************************************/

#define MUX_PORT0 {MUX_A0_WRITE_LO; MUX_A1_WRITE_LO; MUX_A2_WRITE_LO;}

#define MUX_PORT1 {MUX_A0_WRITE_HI; MUX_A1_WRITE_LO; MUX_A2_WRITE_LO;}

#define MUX_PORT2 {MUX_A0_WRITE_LO; MUX_A1_WRITE_HI; MUX_A2_WRITE_LO;}

#define MUX_PORT3 {MUX_A0_WRITE_HI; MUX_A1_WRITE_HI; MUX_A2_WRITE_LO;}

#define MUX_PORT4 {MUX_A0_WRITE_LO; MUX_A1_WRITE_LO; MUX_A2_WRITE_HI;}

#define MUX_PORT5 {MUX_A0_WRITE_HI; MUX_A1_WRITE_LO; MUX_A2_WRITE_HI;}

#define MUX_PORT6 {MUX_A0_WRITE_LO; MUX_A1_WRITE_HI; MUX_A2_WRITE_HI;}

#define MUX_PORT7 {MUX_A0_WRITE_HI; MUX_A1_WRITE_HI; MUX_A2_WRITE_HI;}

#define MUX_DEVICE (MUX_A0_READ_VAL*1 + MUX_A1_READ_VAL*2 + MUX_A2_READ_VAL*4)

unsigned char mux_detect(void);

unsigned char mux_open_port(unsigned char device, unsigned char port);