Service manual

STP 11-25R13-SM-TG
Q - 34
f. Data Flip-Flop (D FF)
.
(1) In the previous FF, outputs were indeterminate. One way to eliminate this is to supply only one
input called the data (D) input. Whichever state (high or low) is present prior to or during the clock will
cause a change in the Q output when the clock pulse appears. Since the output will not change until the
clock pulse arrives, this flip-flop is sometimes called the DELAY FF.
(2) One use for this FF is to store data from a shift register until readout has occurred, allowing the
register to begin its next cycle. Figure Q-31 shows a D FF.
Figure Q-31. Data Flip-Flop