TMS320DM368 Evaluation Module Technical Reference 2011 DSP Development Systems
TMS320DM368 Evaluation Module Technical Reference 514565-0001 Rev. B March 2011 SPECTRUM DIGITAL, INC. 12502 Exchange Drive, Suite 440 Stafford, TX. 77477 Tel: 281.494.4505 Fax: 281.494.5310 sales@spectrumdigital.com www.spectrumdigital.
IMPORTANT NOTICE Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any product or service without notice. Customers are advised to obtain the latest version of relevant information to verify that the data being relied on is current before placing orders. Spectrum Digital, Inc. warrants performance of its products and related software to current specifications in accordance with Spectrum Digital’s standard warranty.
Contents 1 Introduction to the DM368 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides you with a description of the DM368 Evaluation Module, key features, and block diagram. 1.1 Key Features .......................................................... 1.2 Functional Overview of the DM368 EVM ................................. 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.
2.1.1.2.23 Register 720, CCD Internal I/O Direction Register 1 .................... 2.1.1.2.24 Register 721, CCS Internal I/O Read/Write Register 1 .................. 2.1.1.2.25 Register 722, CCD Internal I/O Direction Register 2 .................... 2.1.1.2.26 Register 723, CCD Internal I/O Read/Write Register 2 .................. 2.1.1.2.27 Register 724, CCD Internal I/O Direction Register 3 .................... 2.1.1.2.28 Register 725, CCD Internal I/O Read/Write Register 3 .................. 2.1.1.
3.2.22 J23, I/O Interface Header ............................................ 3.2.23 J24, DILC Host Connector ........................................... 3.2.24 J25, MMC/SD Connector ............................................ 3.2.26 P1, RS-232 UART .................................................. 3.2.27 P2, Ethernet Interface ............................................... 3.2.28 P3, Microphone In .................................................. 3.2.29 P4, Line In .....................................
About This Manual This document describes the board level operations of the DM368 Evaluation Module (EVM). The EVM is based on the Texas Instruments TMS320DM368 Processor. The DM368 Evaluation Module is a table top card that allows engineers and software developers to evaluate certain characteristics of the DM368 processor to determine if the processor meets the designers application requirements. Evaluators can create software to execute on board or expand the system in a variety of ways.
Related Documents, Application Notes and User Guides Information regarding the TMS320DM368 can be found at the following Texas Instruments website: http://www.ti.
Chapter 1 Introduction to the DM368 EVM Chapter One provides a description of the DM368 EVM along with the key features and a block diagram of the circuit board. Topic 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.7.1 1.7.
Spectrum Digital, Inc 1.1 Key Features USB JTAG (14) 1 2 RS-232 SW1 The DM368 EVM is a standalone development platform that enables users to evaluate and develop applications for the TMS320DM368 processor. Schematics, logic equations and application notes are available to ease hardware development and reduce time to market.
Spectrum Digital, Inc • UART Interface • SD/MMC/MS, MMC/SD Media Card Interfaces • 2 Gigabytes NAND Flash • 128 Megabytes of One NAND • AIC3101 stereo codec • USB2 Interface • 10/100 MBS RMII Ethernet Interface • SPI EEPROM • IR Remote Interface via MSP430 • Configurable boot load options • 8 user LEDs/16 user push button switches • Single voltage power supply (+5V) • Expansion connectors for daughter card use • 14 Pin TI JTAG/20 Pin ARM JTAG Interfaces 1-3
Spectrum Digital, Inc The two figures below show the DM368 EVM without the display and with the display mounted.
Spectrum Digital, Inc 1.2 Functional Overview of the DM368 EVM The DM368 on the EVM interfaces to on-board peripherals through the 8/16-bit wide Async EMIF peripheral interface pins. The DDR2 memory is connected to its own dedicated 16 bit wide bus. The Async EMIF bus is also connected to the NAND and One NAND flash. On board video decoders and on chip encoders interface video streams to the DM368 processor. One composite channel and one set of 3 component channel encoder/decoder are standard on the EVM.
Spectrum Digital, Inc 1.4 Memory Map The DM368 processor has a byte addressable address space. There are some limitations to byte addressing which are determined by peripheral interconnection to the DM368 device. Program code and data can be placed anywhere in the unified address space. Addresses are multiple sizes depending on hardware implementation. Refer to the appropriate device data sheets for more details.
Spectrum Digital, Inc Shown below is a break out of the memory spaces. Memory Space Address 0x02000000 NAND Chip Select 0 / One NAND 0x02004000 NAND Chip Select 1 0x40000000 CPLD Control Registers Figure 1-5, DM368 EVM Chip Enable Memory Space 1.5 Boot / Configuration Switch Settings The EVM has a configuration switch that allow users to control the Boot and EMIF configuration state of the processor when it is released from reset. The switch SW4 determines the source for processor booting.
Spectrum Digital, Inc 1.6 Power Supply The EVM operates from a single +5V external power supply connected to the main power input (J7), a 2.5 MM. barrel-type plug. Internally, the +5V input is converted into +1.2 to 1.35V, +1.8V and +3.3V using Texas Instruments TPS65530 power management IC and various linear regulators. The +1.2 to 1.35V supply is used for the DSP core while the +3.3V supply is used for the DSP's I/O buffers and other chips on the board. The +1.
Spectrum Digital, Inc 1.7.1 DM368 UIM Installation on DM368 EVM Checklist To install the DM368 UIM on the DM368 EVM execute the following checklist: o Turn off the power to your DM368 EVM ! o Align connectors J1, J2, and J6 of the UIM with connectors J18, J19,and J23 on the DM368 EVM. J2 to J18 J1 to J19 J6 to J23 Figure 1-6, Align UIM and DM368 EVM Connectors o Visually inspect the alignment of the connectors from the card edge (Spectrum Digital logo) to insure all 6 connectors are mated together.
Spectrum Digital, Inc 1.7.2 Removal of UIM from the DM368 EVM Checklist To remove the UIM from the DM368 EVM execute the following checklist: o Turn off the power to your DM368 EVM ! o Carefully lift the edges of the UIM circuit board up. If necessary rotate lifting from right side, bottom edge, left side, right side, .... until the UIM is free from the DM368 EVM. left bottom right Figure 1-7, Removal of UIM from DM368 EVM o Safely store the UIM in an anti-static bag.
Chapter 2 Board Components This chapter describes the operation of the major board components on the DM368 EVM. Topic 2.1 Asychronous EMIF Interface 2.1.1 NAND Flash 2.1.1.1 One NAND 2.1.1.2 CPLD Interface 2.1.1.2.1 Register 0, CPLD Version 2.1.1.2.2 Register 1, Test Register 2.1.1.2.3 Register 2, LED Register 2.1.1.2.4 Register 3, Board Mux Control Register 2.1.1.2.5 Register 4, Board Switch Register 2.1.1.2.6 Register 5, Power Control Register 2.1.1.2.7 Register 6, GPIO Video Register 2.1.1.2.
Spectrum Digital, Inc Topic 2.1.1.3 2.1.2 2.1.3 2.1.4 2.1.5 2.2 2.2.1 2.2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.8.1 2.9 2.10 2.
Spectrum Digital, Inc 2.1 Asynchronous EMIF Interface An asynchronous 16 bit EMIF with two chip enables divide up the address space and allow for asynchronous accesses on the EVM. This interface connects to the NAND, One NAND, and CPLD registers on the EVM board. 2.1.1 NAND Flash The DM368 has 2 gigabytes of NAND Flash memory mapped into the CE0 space. The NAND Flash memory is used primarily for boot loading and file system on the DM368 EVM.
Spectrum Digital, Inc 2.1.1.2 CPLD Interface The DM368 incorporates an Altera EPM2210, 256 Ball Grid Array (BGA) CPLD. The CPLD incorporates a number of internal registers, glue logic, and I/O multiplexing to allow for a very flexible development platform. The CPLD is accessed via EMIF CE1. The interface is 8 bits wide. All registers show up as 4 mirror images in the memory window due to 32 bit addressing and 8 bit data mapping, that is BA0 and BA1 are not used in the memory decoder for registers.
Spectrum Digital, Inc The following sections describe the registers and their function. A list of the registers is shown in the table below.
Spectrum Digital, Inc 2.1.1.2.1 Register 0, CPLD Version This read only, 8 bit register, contains the 4 bit board type and the 4 bit CPLD version for version control. The default value is 0x21 for the DM368 EVM. 2.1.1.2.2 Register 1, Test Register This read only, 8 bit register, has a default value of 0xA5 and can be read and written to test the memory interface. 2.1.1.2.3 Register 2, LED Register This 8 bit, read/write register controls the user LEDs.
Spectrum Digital, Inc 2.1.1.2.5 Register 4, Board Switch Register This 8 bit, read only register mirrors the values set on switch SW5. These signals are shown in the table below. Table 3: Register 4, Board Switch Register Bit # SW5 Position Signal 7 Reserved N/A 6 Reserved N/A 5 1 SEL_NAND_LOW 0 = NAND mapped to CE0, 1 = ONE NAND mapped to CE0 4 2 SEL_EXTRA1 3 3 SEL_EXTRA2 2 4 SEL_EXTRA3 1 5 CPU_VSEL1 0 = Vcore at 1.2V 1 = Vcore at 1.35 V 0 6 SEL_NTAS_MODE 2.1.1.2.
Spectrum Digital, Inc 2.1.1.2.7 Register 6, GPIO Video Register Register 6 is a 8 bit, read/write register that controls the mapping of GPIO30/32/33, VDIN_WE, DRV_BUS. The default data value is 0b00000000. These controls are shown in the table below.
Spectrum Digital, Inc 2.1.1.2.8 Register 7, Media Card Status Register 7 is a 8 bit, read only register that reads the “Insert” and “Write Protect” status of media cards. These functions of these bits are shown in the table below.
Spectrum Digital, Inc 2.1.1.2.10 Register 9, DILC Input Pin Mapping Register 9 is a 8 bit, read only register that maps DILC pins to read contents on this register. The mapping of these pins is shown in the table below.
Spectrum Digital, Inc 2.1.1.2.12 Register 11, Internal I/O Mux Register 0 Register 11 is a 8 bit, read/write register that controls DM368 GPIO Muxing to IMAGER connector pin input. The default data is 0b00000000. The table below shows this muxing.
Spectrum Digital, Inc 2.1.1.2.14 Register 13, Imager Internal I/O Direction Register 1 Register 13 is a 8 bit, read/write register that controls DM368 GPIO to IMAGER connector pin input/output mapping. The default data is 0b00000000. This mapping is shown in the table below.
Spectrum Digital, Inc 2.1.1.2.16 Register 15, Imager Internal I/O Mux Register 3 Register 14 is a 8 bit, read/write register that controls DM368 GPIO Muxing to IMAGER connector pin input. The default data is 0b00000000. The table below shows this muxing.
Spectrum Digital, Inc 2.1.1.2.18 Register 17, Imager Internal I/O Mux Register 4 Register 17 is a 8 bit, read/write register that controls DM368 GPIO Muxing to IMAGER connector pin input. The default data is 0b00000000. The table below shows this muxing.
Spectrum Digital, Inc 2.1.1.2.20 Imager Multiplexer Mapping The CPLD GPIO functions are incorporated via CPLD control registers mapping selected CPLD/imager pins to DM368 GPIO. Each CPLD mapping function consists of 1 bit Direction control and 2 bits of multiplexer control. Most multiplexing has only 1 or 2 options, but the 2 bits in the multiplexing control were used to allow expansion of options for later revisions.
Spectrum Digital, Inc Table 18: Imager Multiplexer Mapping Pin # B16 B15 2-16 Requires CBT selection override (CPLD Reg and bit) Mux Selection (0)(1) Requires CBT selection override (CPLD Reg and bit) GIO3 Yes, cpld_reg3(3) GIO40 Yes, cpld_reg3(6) GIO92 Yes, cpld_reg3(2)(1)(0) GIO92 Yes, cpld_reg3(2)(1)(0) CPLD Imager IO Dir Bit Imager Name Imager-Mux Bit Mux Selection (0)(1) None (OUTPUT) SPI4_CLK None SPI4_CLK None (OUTPUT) SPI4_SDO None SPI4_SDO cpld_reg16(6) CCD-RST cpld-reg1
Spectrum Digital, Inc 2.1.1.2.21 Register 19, Board RESET/EXTCLK Select Register Register 19 is a 8 bit, read/write register that allows the user to select reset to major external peripherals, and select an external clock for the DM368 EXT PIN (B19). The default data is 0b10000000. The table below shows the mapping of these bits. The external clock on the DM368 CPLD is 74.25 MHz. This clock can be divided and input into the DM368 EXTCLK pin (B19).
Spectrum Digital, Inc 2.1.1.2.22 Register 20, Interrupt Select Register Register 20 is a 8 bit, read/write register that controls the interrupt source to GPIO0 of the DM368 processor. The default data is 0b00000000. The table below shows the mapping of these bits.
Spectrum Digital, Inc 2.1.1.2.24 Register 721, CCD Internal I/O Read/Write Register 1 Register 721 is a 8 bit, read/write register that controls CPLD GPIO input on read, and out value on write. The default data is 0b00000000. The table below shows the mapping of these bits. Table 22: Register 721, CCD Internal I/O Read/Write Register 1 Bit # Signal State Action 7 0 = GPIO_0.7 Write bit when DIR = 0 Read bit when DIR = 1 6 0 = GPIO_0.6 Write bit when DIR = 0 Read bit when DIR = 1 5 0 = GPIO_0.
Spectrum Digital, Inc 2.1.1.2.26 Register 723, CCD Internal I/O Read/Write Register 2 Register 723 is a 8 bit, read/write register that controls CPLD GPIO input on read, and out value on write. The default data is 0b00000000. The table below shows the mapping of these bits. Table 24: Register 723, CCD Internal I/O Read/Write Register 2 Bit # Signal State Action 7 0 = GPIO_0.7 Write bit when DIR = 0 Read bit when DIR = 1 6 0 = GPIO_0.6 Write bit when DIR = 0 Read bit when DIR = 1 5 0 = GPIO_0.
Spectrum Digital, Inc 2.1.1.2.28 Register 725, CCD Internal I/O Read/Write Register 3 Register 725 is a 8 bit, read/write register that controls CPLD GPIO input on read, and out value on write. The default data is 0b00000000. The table below shows the mapping of these bits. Table 26: Register 725, CCD Internal I/O Read/Write Register 1 Bit # Signal State Action 7 0 = GPIO_0.7 Write bit when DIR = 0 Read bit when DIR = 1 6 0 = GPIO_0.6 Write bit when DIR = 0 Read bit when DIR = 1 5 0 = GPIO_0.
Spectrum Digital, Inc 2.1.2 DDR2 Memory Interface The DM368 device incorporates a dedicated 16 bit wide DDR2 memory bus. The EVM uses a single 1 gigabit 16 bit wide memory on this bus, for a total of 128 megabytes of memory for program, data, and video storage. The internal DDR controller uses a PLL to control the DDR memory timing. Memory refresh for DDR2 is handled automatically by the DM368 internal DDR controller. 2.1.
Spectrum Digital, Inc 2.2 Input Video Port Interfaces/Imager Input Ports The DM368 EVM supports composite, component, or imager video capture. CBT multiplexers selected via CPLD registers chose the interface that is connected to the DM368 video input port. A Texas Instruments TVP5146 is used to decode composite video or S-video inputs into the device. J15 is used for the S-video inputs and J13 for the composite inputs on the EVM. A TVP7002 provides component image capture up to 720P resolution.
Spectrum Digital, Inc 2.3 AIC3101 Interface The EVM uses a Texas Instruments TLV320AIC3101 stereo codec for input and output of audio signals. The codec samples analog signals on the microphone or line inputs and converts them into digital data so it can be processed by the DSP. When the DSP is finished with the data it uses the codec to convert the samples back into analog signals on the line output so the user can hear the output.
Spectrum Digital, Inc 2.4 On Chip Voice Codec The DM368 integrates a single channel voice codec. The input for this codec is connected to on board microphone M1. The output of this codec is connected to on board speaker SPK1. 2.5 On Chip Analog to Digital Converter (ADC) The DM368 has an on chip 6 channel Analog to Digital Converter (ADC). Four of the channels are interfaced to on board voltages and two channels are connected to test points as shown in the table below.
Spectrum Digital, Inc 2.7 Ethernet Interface The DM368 incorporates an internal MII ethernet MAC which interfaces to a Mircel 10/100 ethernet Phy. The 10/100 Mbit interface is isolated and brought out to a RJ-45 standard ethernet connector, P2. The ethernet address is stored in the on board I2C EEPROM manufacturing. For GPIO modes of operation when the MII interface is not used CBTLV multiplexes and directs the I/O to the on board CPLD used as imager expansion I/Os.
Spectrum Digital, Inc 2.8.1 MSP430 The DM368 EVM incorporates infrared remote, interface using a MSP430 microcontroller. The I2C interface is used on the DM368 processor to communicate to the MSP430. The MSP430 acts as a slave device on the I2C bus. 2.9 Daughter Card Interfaces The EVM provides expansion connectors that can be used to accept plug-in daughter cards.
Spectrum Digital, Inc 2.11 Battery The DM368 EVM incorporates a battery holder to provide backup power to the internal real time clock when the power is not applied to the board. The optional battery should be +3 volt 20 millimeter coin type Lithium single cell. Some common part numbers for batteries which should operate in the EVM are shown in the table below.
Chapter 3 Physical Description This chapter describes the physical layout of the DM368 EVM and its interfaces. Topic 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.2.10 3.2.11 3.2.12 3.2.13 3.2.14 3.2.15 3.2.16 3.2.17 3.2.18 3.2.19 3.2.20 3.2.21 3.2.22 3.2.23 3.2.24 3.2.26 3.2.27 3.2.
Spectrum Digital, Inc Topic 3.2.29 3.2.30 3.2.31 3.2.32 3.2.33 3.2.34 3.2.35 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.
Spectrum Digital, Inc 3.1 Board Layout The DM368 EVM is a 8.0 x 8.7 inch (203 x 221 mm.) ten (10) layer printed circuit board which is powered by an external +5 volt only power supply. Figure 3-1 shows the layout of the top side of the DM368 EVM.
Spectrum Digital, Inc Figure 3-2 shows the layout of the bottom side of the DM368 EVM.
Spectrum Digital, Inc 3.2 Connectors The DM368 EVM has numerous connectors, option jumpers, and interfaces to control and provide connections to various peripherals. These connectors and jumpers are described in the following sections.
Spectrum Digital, Inc 3.2.1 J1, USB MiniAB Connector and Jumpers Connector J1 is a mini A/B USB connector. The pinout for the J1 connector is shown in the table below. Table 2: J1, MiniAB USB Connector Pins Signal 1 USB_VBUS_CONN 2 USB_DM 3 USB_DP 4 USB_ID 5 GND The EVM incorporates the ability to toggle the ID pin on the USB connector via software control. The USB_ID pin on the DM368 controls this function. For “USB ON The Go” mode remove jumper J6.
Spectrum Digital, Inc 3.2.2 J2, 14 Pin External JTAG Connector Connector J2 is a 2 x 7 double row male header with pin 6 clipped to serve as a key. This is the standard interface used by JTAG emulators to interface to Texas Instruments processors. The pinout for the connector is shown in the figure below. TMS TDI PD (+3.3V) TDO TCK-RET TCK EMU0 1 3 5 7 9 11 13 2 4 6 8 10 12 14 TRSTGND no pin (key) GND GND GND EMU1 Header Dimensions Pin-to-Pin spacing, 0.100 in. (X,Y) Pin width, 0.025-in.
Spectrum Digital, Inc 3.2.3 J3, MSP430 JTAG Header The J3, MSP430 JTAG header, is located on the top side of the board and is used to provide a programming interface to the MSP430 microcontroller. The pinout for the J3 connector is shown in the table below. This connector is typically used for factory use only.
Spectrum Digital, Inc 3.2.5 J5, 20 Pin ARM JTAG Emulation Header The J5 emulation header is located on the top side of the board and is used to provide an interface to ARM compatible JTAG emulators. The pinout for this connector is shown in the table below.
Spectrum Digital, Inc 3.2.7 J7, +5 Volts Input Connector J7 is the input power connector. This connector brings in +5 volts to the EVM. This is a 2.5mm. jack. The inside of the jack is tied to through a fuse to VCC_5V. The other side is tied to ground and LED DS1. The figure below shows this connector as viewed from the card edge. +5V J7 Ground PC Board Front View Figure 3-6, J7, +5 Volt Input Connector 3.2.
Spectrum Digital, Inc 3.2.9 J10, Imager Interface Connector J10 is 32 x 3 connector used to interface to external imager logic. The pin out for this connector is shown in the table below.
Spectrum Digital, Inc 3.2.
Spectrum Digital, Inc 3.2.11 J8, Y Component Video In, RCA Jack (Green) J8 is an RCA jack used as a Y component input to the THS7353, U15, pin 3. The figure below shows this connector as viewed from the card edge. Pin 1,3,4 Shield (ground) Pin 2, Signal Input Figure 3-7, J8, Y Component Video In, RCA Jack Table 10: J8, Y Component Video In, RCA Jack Pin # Signal Name 1 TVP_AGND 2 CH2-INA, U15, Pin 3 3 TVP_AGND 4 TVP_AGND 3.2.
Spectrum Digital, Inc 3.2.13 J11, Pr Component Video In, RCA Jack (Red) J11 is an RCA jack used as a Pr component input to the THS7353, U15, pin 2. The figure below shows this connector as viewed from the card edge. Pin 1,3,4 Shield (ground) Pin 2, Signal Input Figure 3-9, J11, Pr Component Video In, RCA Jack Table 12: J11, Pr Component Video In, RCA Jack Pin # Signal Name 1 TVP_AGND 2 CH1-INA, U15, Pin 2 3 TVP_AGND 4 TVP_AGND 3.2.
Spectrum Digital, Inc 3.2.15 J13, CVBS/Y Input, RCA Jack (Yellow) J13 is an RCA jack used as the CVBS/Y input to the TVP5146. The figure below shows this connector as viewed from the card edge. Pin 1,3,4 Shield (ground) Pin 2, Signal Input Figure 3-11, J13, CVBS/Y Input, RCA Jack Table 14: J13, CVBS/Y Input, RCA Jack Pin # Signal Name 1 DEC_GND 2 VI_2_B, U24, Pin 8, TVP5146 3 DEC_GND 2 DEC_GND 3.2.16 J16, Composite TV Out, RCA Jack (Yellow) J16 is an RCA jack used as a TV output from the DM368.
Spectrum Digital, Inc 3.2.17 J17, Y Component Video Out, RCA Jack (Green) J17 is an RCA jack used as a green component output from the THS7303 DAC, U23, pin 17, signal CH2-OUT. The figure below shows this connector as viewed from the card edge. Pin 1,3,4 Shield (ground) Pin 2, Signal Input Figure 3-13, J17, Y Component Video Out, RCA Jack Table 16: J17, Y Component Video Out, RCA Jack Pin # Signal Name 1 DENC_GND 2 THS7303 DAC, U23, pin 17,signal CH2-OUT 3 DENC_GND 4 DENC_GND 3.2.
Spectrum Digital, Inc 3.2.19 J21, Pr Component Video Output, RCA Jack (Red) J21 is an RCA jack used as a Pr component output from the THS7303 DAC, U23, pin 19, signal CH1-OUT. The figure below shows this connector as viewed from the card edge.
Spectrum Digital, Inc 3.2.20 J18, J19, Video Output DC Connectors J18 and J19 make up the interface to the video output DC interface. The signals on each of these connectors are shown in the tables below.
Spectrum Digital, Inc 3.2.21 J22, CPLD Programming Header The J22, CPLD programming header, is for use by the factory. This header is not intended to be used outside the factory. The signals on this header are shown in the table below. Table 21: J22, CPLD Programming Header Pins Signal Pins Signal 1 ISR_TCK 2 Ground 3 ISR_TDO 4 VCC_3V3 5 ISR_TMS 6 NC 7 NC 8 NC 9 ISR_TDI 10 Ground 3.2.
Spectrum Digital, Inc 3.2.23 J24, DILC Host Connector J24 is the DILC Host Connector. The signals on this connector are shown in the table below.
Spectrum Digital, Inc 3.2.24 J25, MMC/SD Connector The J25 MMC/SD connector is located on the bottom side of the board and is used to provide an interface to a MMC/SD card. The pinout for the J25 connector is shown in the table below.
Spectrum Digital, Inc 3.2.26 P1, RS-232 UART The P1 connector is a 9 pin male D-connector which provides a UART interface to the EVM. This connector interfaces to the MAX 3221 RS-232 line driver (U3) and is located on the top side of the board. A view of the connector from the card edge is shown in the figure below. The signals present on this connector are defined in the following table.
Spectrum Digital, Inc 3.2.27 P2, Ethernet Interface The P2 connector is located on the top side of the board and is used to provide an Ethernet interface. P2 integrates the magnetics and standard RJ-45 connector. The two tables below show the signals present on the magnetics interface and the connector side.
Spectrum Digital, Inc 3.2.28 P3, Microphone In The microphone input, P3, is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is monaural. The signal is connected to signals “MIC2R” and “MIC2L” of the TVL320AIC3101. The signals on the plug are shown in the figure below.
Spectrum Digital, Inc 3.2.30 P5, Line Out The connector P5, is an audio stereo output from the TVL320AIC3101, U7, on the EVM. The output connector is a 3.5 mm stereo jack. The signals on the mating plug are shown in the figure below. Ground (sleeve) Right Line Out (ring) Left Line Out (tip) Figure 3-19, P5, Audio Line Out Stereo Jack Table 30: P5, Audio Line Out Stereo Jack Pin # AIC3101 Signal 1 GND_AIC 2 LEFT_LO+, U7, Pin 27 3 RIGHT_LO+, U7, Pin 29 4 NC 3.2.
Spectrum Digital, Inc 3.2.32 U1, Infrared Interface U1 is an infrared receiver mounted on the edge of the board. This device interfaces to the MSP430 mircrocontroller. The view of U1 is shown from a board edge view in the figure below. U1 PC Card Figure 3-21, U1, IR Interface, Card Edge View The receiver supports interaction with an Infrared remote control included with your EVM. Table 32: U1, Infrared Interface U1 Pin # MSP430 Signal, Pin # 1 P1.2/TA1/A1+/A4-, U2, Pin 4 2 GND 3 VCC_3V3 3.2.
Spectrum Digital, Inc 3.2.34 BHT1, Battery Interface BHT1 is a holder for a BA2032SM battery. The signals on each pin are shown below in the table below. Table 34: BHT1, Battery Interface BHT1 Pin # BHT1 Connection 1 VBK, U9, Pin 13 2 Ground 3.2.35 M1, Microphone Interface The microphone interface, M1, provides a microphone input directly into the DM368 processor. The connections going to the processor are shown in the table below.
Spectrum Digital, Inc 3.3 LEDs The EVM has nine (9) LEDs which are located on the top side of the board. Information regarding the LEDs are shown in the table below.
Spectrum Digital, Inc 3.4 Switches The EVM has twenty-three (23) switches. The function of these switches are shown in the table below.
Spectrum Digital, Inc 3.4.1 SW1, EMU0/1 Select Switch SW1 is a 2 position DIP switch providing 4 options in selecting the state of the EMU0 and EMU1 pins on the TMS320DM368 processor. A view of the switch is shown in the figure below. The selection options with this switch are in the table below.
Spectrum Digital, Inc 3.4.4 SW4, Boot Mode / Configuration Select Switch SW4 is a 6 position DIP switch used to select the ARM Boot Mode and processor configuration. The first 3 positions selection the ARM boot mode. The last 3 positions select the processor configuration. The figure and tables below show these options.
Spectrum Digital, Inc 3.4.5 SW5, Board Configuration Select Switch SW5 is a 6 position switch that configures specific board functions. The figure below shows the switch as it appears on the EVM. SW5 NAND /ONE NAND EXTRA1 EXTRA2 EXTRA3 VCORE ADJUST NTSC / PAL Elevated Actuator OFF ON Figure 3-24, SW5, Board Configuration Select The table below shows the function of each switch position on SW5.
Spectrum Digital, Inc 3.4.6 SW6 - SW21, Function Pushbuttons Switches SW6 through SW21 are push button momentary switches that are inputs in to the DM368 processor. These switches can be read with software and their function is determined by the application. 3.4.7 SW22, MSP430 IO0 Pushbutton Switch SW22 is a push button momentary switch reserved for future use. 3.4.
Spectrum Digital, Inc 3.5 Jumpers The following section describes the jumpers on the DM368 EVM. 3.5.1 JP1, Jumper Block Jumper block JP1, found on schematic page 39, allows the user to connect signals from the DM368 processor to the TVL320AIC3101, U7. The signals on this 9 x 2 header are shown in the table below.
Spectrum Digital, Inc 3.5.4 J26, USB ID Select The J26 jumper is used to pull the USB_ID line on USB connector high or low. The selections are shown below. ID H J26 H L ID L J26 Pos 2-3 View Pos 1-2 View Figure 3-26, J26, USB ID Select Table 44: J26, USB ID Select Position Function 1-2 USB_ID pulled high * 2-3 USB_ID pulled low * Factory shipped configuration 3.5.5 J27, U14 LL8 Voltage Select The J27 jumper is used to select the voltage input to U14, Pin 27, LL8.
Spectrum Digital, Inc 3.6 Test Points The EVM has 65 test points. The following 2 figures identify the position of each test point. The next two tables lists each test point and the signal appearing on that test point.
Spectrum Digital, Inc TP53,TP54 Figure 3-29, DM368 EVM, Bottom Side Test Points 3-37
Spectrum Digital, Inc Table 46: DM368 EVM Test Points 3-38 TP # Schematic Page Signal TP # Schematic Page TP1 52 GND TP46 20 U33A, F2, B1.IO_21 TP2 52 GND TP47 23 U33D, P11, B4.IO_47 TP5 52 VCC_5V TP48 23 U33D, P7, B4.IO_21 TP6 44 U2, Pin 6, MP430_IO2 TP49 20 U33A, M4, B1.IO_58 TP7 43 U5, Pin 25, INT#PHYAD0 TP50 20 U33A, P2, B1.
Spectrum Digital, Inc There are 18 power test points on the EVM. These test points provide a convenient mechanism to check the EVM’s multiple power supplies. The table below shows the voltages for each test point and what the supply is used for. Table 47: Power Test Points Access Test Point Schematic Page Voltage Shunt Power Domain T1 13 +1.8V 0.02 ohms VCC_1V8, U18-14, R12, CPU_VDD_DDR TP9 13 +3.3V 0.02 ohms VCC_3V3, U18-14, P5, CPU_VDDSHV TP11 13 +1.2V 0.
Spectrum Digital, Inc 3-40 DM368 EVM Technical Reference
Appendix A Schematics This appendix contains the schematics for the DM368 EVM.
A-2 A B C D A A 4 A 3 A 2 E 1 REV SHEET 5 14 A 12 A 13 A A 11 24 SHEET 23 A 33 A A 34 A A 44 43 A A 5 6 A 16 A A A 26 A 36 A 46 15 25 A 35 A 45 A REVISION STATUS OF SHEETS REV 22 21 32 SHEET 31 SHEET A A REV 42 A 41 SHEET A REV A REV 5 7 A 17 A 27 A 37 A 47 A A 8 A 18 A 28 A 38 A 48 A 9 A 19 A 29 A 39 A 49 A 10 A 20 A 30 A 40 A 50 APPLICATION NEXT ASSY 4 USED ON 4 RLSE MFG QA ENGR-MG
A B C D DDR_STRBEN_DEL DDR_STRBEN R277 10 T_DDR_STRBEN 5 4 DDR_CLK DDR_CLK DDR_CKE DDR_WE DDR_CAS DDR_RAS DDR_CS DDR_BA[2] DDR_BA[1] DDR_BA[0] DDR_A01 DDR_A00 DDR_A09 DDR_A08 DDR_A07 DDR_A06 DDR_A05 DDR_A04 DDR_A03 DDR_A02 DDR_A13 DDR_A12 DDR_A11 DDR_A10 DDR_VREF DDR_PADREFP TMS320DM368 DDR_GATE1 DDR_GATE0 DDR_DQSN[0] DDR_DQS[0] DDR_DQSN[1] DDR_DQS[1] DDR_DQM[0] DDR_DQM[1] DDR_DQ0 DDR_DQ1 DDR_DQ2 DDR_DQ3 DDR_DQ4 DDR_DQ5 DDR_DQ6 DDR_DQ7 DDR_DQ8 DDR_DQ9 DDR_DQ10 DDR_
A-4 A B C D EM_D15 EM_D14 EM_D13 EM_D12 EM_D7 EM_D6 EM_D5 EM_D4 EM_D3 EM_D2 EM_D1 EM_D0 20,25,26,27 20,25,26,27 20,25,26,27 20,25,26,27 20,25,26,27 20,25,26,27 20,25,26,27 20,25,26,27 25,27 EM_D11 25,27 EM_D10 25,27 EM_D9 25,27 EM_D8 25,27 25,27 25,27 25,27 25,26,27 EM_WAIT 5 EM_A13 EM_A12 EM_A11 EM_A10 EM_A9 EM_A8 R360 20K T_EM_D3 T_EM_D2 T_EM_D1 T_EM_D0 T_EM_D7 T_EM_D6 T_EM_D5 T_EM_D4 T_EM_D11 T_EM_D10 T_EM_D9 T_EM_D8 T_EM_D15 T_EM_D14 T_EM_D13 T_EM_D12 T_EM_WAIT R361 20K EM_D3 EM_D2
A B C C33 C34 1.0uF 1.0uF CPU_VCC_1V8 CPU_VCC_3V3 5 C167 0.01uF C168 0.01uF R43 R42 2 1 2 0.02 0.02 TP13 1 TP12 4 4 E3 NFM21PC474R1C3D 1 3 C200 0.01uF E2 NFM21PC474R1C3D 1 3 2 2 D 5 C209 0.01uF C210 0.001uF .22uF C219 C199 0.01uF C47 0.
A-6 A B C D 5 5 VDIN_C7 VDIN_C6 VDIN_C5 VDIN_C4 VDIN_C3 VDIN_C2 VDIN_C1 VDIN_C0 33 33 33 33 33 33 33 33 VDIN_VD 33 VDIN_PCLK 21 VDIN_WEN 33 33 VDIN_HD VDIN_Y7 VDIN_Y6 VDIN_Y5 VDIN_Y4 VDIN_Y3 VDIN_Y2 VDIN_Y1 VDIN_Y0 33 33 33 33 33 33 33 33 0 4 R291 VDIN_PCLK 0 B14 D13 E13 C14 R337 VDIN_WEN VDIN_HD A15 C15 B16 A16 A17 C16 A18 B17 VDIN_C7 VDIN_C6 VDIN_C5 VDIN_C4 VDIN_C3 VDIN_C2 VDIN_C1 VDIN_C0 VD IN_VD C12 A13 B13 D12 A14 B15 D14 D15 VDI N_Y7 VDI N_Y6 VDI N_Y5 VDI N_Y4 VDI N_Y3 V
A B C D U18-2 5 TMS320DM368 YOUT7(R7) YOUT6(R6) YOUT5(R5) YOUT4(R4) YOUT3(R3) YOUT2(G7) YOUT1(G6) YOUT0(G5) GIO92/COUT7(G4)/PWM0 GIO91/COUT6(G3)/PWM1 GIO90/COUT5(G2)/PWM2/RTO0 GIO89/COUT4(B7)/PWM2/RTO1 GIO88/COUT3(B6)/PWM2/RTO2 GIO87/COUT2(B5)/PWM2/RTO3 GIO86/COUT19B4)/PWM3/STTRIG GIO85/COUT0(B3)/PWM3 FIELD LCD_OE/GIO82 VSYNC/GIO83 HSYNC/GIO84 GIO80/EXTCLK/B2/PWM3 VCLK/GIO79 5 CPU_COUT7 CPU_COUT6 CPU_COUT5 CPU_COUT4 CPU_COUT3 CPU_COUT2 CPU_COUT1 CPU_COUT0 CPU_YOUT7 CPU_YOUT6 CPU_YOUT5 CPU_YOUT4
A B C C334 2.2uF VCC_1V2 C314 2.2uF CPU_VCC_1V8 5 R103 R95 L22 2 0.02 L27 2 0.02 BLM21B050S 1 TP44 BLM21B050S 1 TP43 2 1 DSP_GND 4 R475 1K DAC_3V3 E10 NFM21PC474R1C3D 1 3 C83 10uF 4 C95 0.01uF C77 0.01uF C101 270pF 4 R120 3 0 C76 .1uF C416 1uF DSP_GND R474 C93 .1uF R125 DSP_GND 7.5K R476 4.
A B C D 5 20 SEL_SD1n_GPIO 31 CONN_SD1_DATA3 20 CPU_GPIO41 31 CONN_SD1_DATA2 20 CPU_GPIO40 31 CONN_SD1_DATA1 20 CPU_GPIO39 31 CONN_SD1_DATA0 20 CPU_GPIO38 CPU_GPIO42 31 CONN_SD1_CMD 20 CPU_GPIO42 R265 2K SEL_SD1n_GPIO CPU_GPIO38 CPU_GPIO39 CPU_GPIO40 CPU_GPIO41 SEL_SD1n_GPIO CPU_GPIO43 31 CONN_SD1_CLK 20 CPU_GPIO43 5 S OE 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 GND 4A 3A 2A 1A VCC 8 12 S OE 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 GND 4A 3A 2A 1A VCC 8 12 9 7 4 16 SN74CBTLV3257PW 1
A-10 A B C D 5 20 PWM0 20 PWM1 20 GIO33_CPU 5 R531 28 SPI0_SDENA0 28 SPI0_SCLK 28 SPI0_SDI 28 SPI0_SDO R530 40 SPI1_SDENA0 40 SPI1_SCLK 40 SPI1_SDI 40 SPI1_SDO 0 20 GIO32_CPU 20 GIO31_CPU 20 GIO30_CPU 20 GPIO0 GIO33_CPU R469 2.
A B C 14 DSP_PWCTR_OUT0 21 CPU_RESETn 5 360 NO-POP R262 R482 R257 10K R258 NO-POP VCC_3V3 4 19 CPU_EMU1 19 CPU_EMU0 19 CPU_TRSTn 19 CPU_TMS 19 CPU_TDO 19 CPU_TDI 19 CPU_RTCK 19 CPU_TCK 4 TEST POINT_0 TP26 DM360_RESETn 1 3 H4 G5 H5 G2 G4 F5 F2 F4 H3 3 VSS_MXI MXO1 MXI1 VDDMXI TMS320DM368 EMU1 EMU0 TRST TMS TDO TDI RTCK TCK RESET U18-13 L2 K1 L1 L6 C227 0.1uF C225 0.
A-12 A B C D R78 R83 R87 R77 5 TEST POINT 1 TP36 TEST POINT 1 TP37 VCC_1V2 R80 CPU_VCC_1V8 VCC_3V3 R89 CCD_PSMON R315 1K R287 1K R292 1K R311 1K R300 1K R283 1K AGND_DM360 1K AGND_DM360 1K AGND_DM360 1K AGND_DM360 1K AGND_DM360 1K AGND_DM360 1K 4 4 A6 D7 D8 A7 B7 E8 VSSA_ADC VDDA18_ADC TMS320DM368 ADC_CH5 ADC_CH4 ADC_CH3 ADC_CH2 ADC_CH1 ADC_CH0 U18-10 F8 G9 C54 1uF 3 AGND_DM360 3 C198 0.
A B C D BLM21B050S C224 0.01uF L73 C169 1.0uF 5 BLM21B050S C193 0.01uF L59 VCC_1V8 CPU_VCC_1V8 C343 1.0uF VCC_3V3 CPU_VCC_3V3 E6 NFM21PC474R1C3D 1 3 E1 NFM21PC474R1C3D 1 3 2 2 C203 0.01uF R53 C215 0.01uF R61 2 0.02 1 2 0.02 TP22 1 TP29 C60 0.1uF C55 0.1uF 4 AGND_DM360 C207 0.01uF AGND_DM360 C216 0.
A-14 A B C D C31 4.7uF C348 2.2uF C315 2.2uF C87 4.7uF 5 C324 2.2uF CPU_VCC_3V3 C86 4.7uF CPU_VCC_1V8 C192 2.2uF CPU_VCC_1V8 C96 4.7uF CPU_VCC_1V8 C164 2.2uF VCC_1V3 VCC_1V2 1 1 C318 1.0uF T1 1 R92 2 2 2 0.02 1 R94 2 1 0.02 TP42 C309 1.0uF 0.02 C206 0.1uF 0.02 C333 1.0uF TP17 R104 R242 2 TP45 C171 1.0uF R45 TP15 0.02 CPU_VDDSHV10 CPU_VDD_DDR CPU_VDDS C194 2.
A B C D C191 2.2uF R470 VCC_3V3 5 1 SW2 B B1 0 0.02 0.02 C205 0.1uF R274 R273 2 TP18 R241 PUSHBUTTON SW A A1 47 TPS65510_CS 47 TPS65510_XRESET 1V8_BB_UP C190 1.0uF 1 R240 2 TP19 TP63 R471 JP29 HEADER 2(NO-POP) 20K 0 C211 0.1uF 0 R472 10K 0.1uF C415 PWCTRIO6 PWCTRIO5 PWCTRIO4 PWCTRIO3 PWCTRIO2 PWCTRIO1 PWCTRIO0 PWCTRO3 PWCTRO2 PWCTRO1 PWCTRO0 VDD GND RESET 2 1 6 4 2 JP2 2 0.
A-16 A B C D 5 5 TMS320DM368 U18-15 VSS W1 4 4 W19 A19 N14 F14 E14 P13 J13 N12 G12 M11 L11 K11 J11 G11 L10 K10 J10 H10 M9 L9 K9 J9 H9 P8 N8 M8 L8 M7 L7 U18-12 VSS.1 VSS.2 VSS.3 VSS.4 VSS.5 VSS.6 VSS.7 VSS.8 VSS.9 VSS.10 VSS.11 VSS.12 VSS.13 VSS.14 VSS.15 VSS.16 VSS.17 VSS.18 VSS.19 VSS.20 VSS.21 VSS.22 VSS.23 VSS.24 VSS.25 VSS.26 VSS.27 VSS.28 VSS.
A B C D 5 CPU_VDDS 5 C281 0.01uF C78 10uF CPU_VDD_DDR C284 0.01uF CPU_VDD_DDR C68 10uF CPU_VDD C305 0.01uF CPU_VDD 6 C226 0.01uF C79 10uF C276 0.01uF C80 10uF C302 0.01uF C285 0.01uF C282 0.01uF C304 0.01uF C267 0.01uF C270 0.01uF C81 10uF C296 0.01uF C256 0.01uF C229 0.01uF C248 0.01uF C263 0.01uF C252 0.01uF C228 0.01uF 4 C255 0.01uF 15 4 C253 0.01uF C289 0.01uF C303 0.01uF CPU_VDDSHV10 C237 0.01uF C293 0.01uF C292 0.01uF 3 3 C272 0.01uF C262 0.
A-18 A B C D 2 VREF_STL C61 2.2uF 3 5 VREF_STL C230 4.7uF E8 NFM21PC474R1C3D 1 5 2 CPU_VCC_1V8 C234 0.01uF R304 1K 1% R293 1K 1% DDR_VDD C233 0.01uF C268 0.01uF C283 0.01uF DDR_VDD 4 Layout for the 92-ball DDR Package but populate the 84-ball MT47H64M16HR-3:E. 84 Ball memories resisde in the center section of the 92 Ball Package C274 0.1uF C266 0.1uF C236 0.01uF DDR_VDD 4 R303 C235 0.01uF 0 C286 0.01uF C269 0.01uF U19 VSSQ.1 VSSQ.2 VSSQ.3 VSSQ.4 VSSQ.5 VSSQ.6 VSSQ.7 VSSQ.
A B C 5 USB_DM USB_DP USB_ID 4 4 4 23 DRV_VBUS U SB_ID USB_DM USB_DP DRV_VBUS C135 NO-POP 4 DIFFERENTIAL PAIR 90 OHM DIFFERENTIAL IMPEDANCE SHORT AND STRAIGHT AS POSSIBLE, MINIMUM NUMBER OF VIAS R8 10uF +C136 VCC_5V 0 GND 1 2 3 HEADER 3 J26 R7 10K U4 IN1 IN2 R6 NO-POP VCC_3V3 TPS2065D 1 2 3 3 8 7 6 R468 0 R467 1.
A-20 A B C D 5 R159 2.
A B C D 9 9 5 1 TP50 TEST POINT PWM0 1 TP49 TEST POINT PWM1 TP46 TEST POINT 5 1 9,28,32,34,35,36,37,39,40,44 I2C_DATA 9,28,32,34,35,36,37,39,40,44 I2C_SCLK 3,25,26,27 EM_D7 3,25,26,27 EM_D6 3,25,26,27 EM_D5 3,25,26,27 EM_D4 3,25,26,27 EM_D3 3,25,26,27 EM_D2 3,25,26,27 EM_D1 3,25,26,27 EM_D0 26 NAND_CE0n 26 NAND_CE1n 27 ONENAND_CE 9 SPI4_SCLK 9 SPI4_SDI_GPIO_MD2 9 SPI4_SDO 8 SEL_SD1n_GPIO 9 GPIO0 9 GPIO37 9 GIO33_CPU 9 GIO32_CPU 9 GIO31_CPU 9 GIO30_CPU 8 CPU_GPIO38 8 CPU_GPIO39 8 CPU_GPIO40
A-22 A B C D VCC_3V3 R401 R400 R399 R398 R397 R396 5 1K 1K 1K 1K 1K 1K 5 1 2 3 4 5 6 6 5 4 3 2 1 12 11 10 9 8 7 DIP_SWITCH_6 SW5 R373 10K R372 10K R370 10K 4 10 CPU_RESETn 46 PB_SWITCH 19 ARM_RSTn R368 10K 48 SEL_EXTRA_3 48 CPU_VSEL1 R369 10K 33 CPLD_CCD-DATA01 33 CPLD_CCD-DATA00 R371 10K 4 48 EN7 48 ENAFE 48 SEQ56 48 EN56 49 ENABLE_LCD_15V 42 CPU_GPIO17 42 CPU_GPIO16 42 CPU_GPIO15 42 CPU_GPIO14 42 CPU_GPIO13 42 CPU_GPIO12 42 CPU_GPIO11 42 CPU_GPIO10 42 CPU_GPIO9 42 CPU_GPIO8
A B C D 5 38 CPLD_McBSP_CLKX 38 CPLD_McBSP_FSX 38 CPLD_McBSP_DX 38 CPLD_McBSP_CLKR 38 CPLD_McBSP_FSR 38 CPLD_McBSP_DR 38 SEL_AICn_GPIO 33 CPLD_CCD-DATA02 46 LED4 46 LED5 46 LED6 46 LED7 33 CPLD_CCD-DATA03 33 DECODER_IMAGER_S0 33 DECODER_IMAGER_S1 33 DECODER_IMAGER_S2 6,40 VDOUT_C7 6,40 VDOUT_C6 6,40 VDOUT_C5 6,40 VDOUT_C4 6,40 VDOUT_C3 6,40 VDOUT_C2 6,40 VDOUT_C1 6,40 VDOUT_C0 34 PWM_CCD_SUB 34 CCD-DDSRST 34 GPIO_MST_SLV 34 GPIO_TACH 34 GPIO_MD19 34 GPIO_MD18 34 GPIO_MD17 34 GPIO_MD16 34 GPIO_MD15 34 G
A-24 A B C D 5 TP47 TEST POINT TP48 TEST POINT 5 1 1 41 GIO_DILC_DOCK_DET 41 GIO_DILC_CAM_PWR_DET 41 SPI2_SCLK_DILC 41 SPI2_SDO_DILC 41 SPI2_SDI_DILC 41 GIO_DILC_AVJDET 41 GIO_DILC_CHG_CTL 41 GIO_DILC_DRV_VBUS1 41 GIO_DILC_VBUS_DET 3 EMIF_KEYPAD 30 MS.INS 30 SD/MMC.INS 30 SD/MMC.WP 31 SD/MMC1.WP 31 SD/MMC1.INS 40 CPLD.CONN_RESETn 40 CPLD.CONN_GIO6 40 CPLD.CONN_GIO16 40 CPLD.CONN_GIO54 40 CPLD.CONN_GIO65 40 CPLD.CONN_GIO63 40 CPLD.CONN_GIO62 40 CPLD.CONN_GIO60 40 CPLD.CONN_GIO58 40 CPLD.
A B C D 5 5 VCC_CPLD_1V8 F10 G11 H8 H10 J7 J9 K6 L7 4 EPM2210GF256C5N VCCINT.1 VCCINT.2 VCCINT.3 VCCINT.4 VCCINT.5 VCCINT.6 VCCINT.7 VCCINT.8 U33E 4 GNDIO.1 GNDIO.2 GNDIO.3 GNDIO.4 GNDIO.5 GNDIO.6 GNDIO.7 GNDIO.8 GNDIO.9 GNDIO.10 GNDIO.11 GNDIO.12 GNDIO.13 GNDIO.14 GNDIO.15 GNDIO.16 GNDINT.1 GNDINT.2 GNDINT.3 GNDINT.4 GNDINT.5 GNDINT.6 GNDINT.7 GNDINT.8 A1 A16 B2 B15 G7 G8 G9 G10 K7 K8 K9 K10 R2 R15 T1 T16 F7 G6 H7 H9 J8 J10 K11 L10 3 C420 10uF VCC_CPLD_1V8 C388 0.
A-26 A B C D 5 3,20 EMIF_SEL 5 R413 10K EM_D0 EM_D2 EM_D4 EM_D6 3,27 EM_A6 3,20,27 EM_A8 3,20,27 EM_A10 3,20,27 EM_A12 3,27 EM_BA0 3,27 EM_A0 3,20,26,27 EM_A2 3,27 EM_A4 3,20 EM_CE1 3,20 EM_CE0 3,26,27 EM_WAIT 3,27 EM_D8 3,27 EM_D10 3,27 EM_D12 3,27 EM_D14 3,20,26,27 3,20,26,27 3,20,26,27 3,20,26,27 EM_CE1 VCC_5V VCC_3V3 EM_A6 EM_A8 EM_A10 EM_A12 4 EM_CE0 EM_D8 EM_D10 EM_D12 EM_D14 EM_D0 EM_D2 EM_D4 EM_D6 EM_BA0 EM_A0 EM_A2 EM_A4 4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
A B C 5 3,20,25,27 EM_OE 20 NAND_CE0n 20 NAND_CE1n 4 C369 0.1uF VCC_3V3 NAND_CLE NAND_ALE EM_WE R391 R389 NAND_RE NAND_CE0n NAND_CE1n R114 10K VCC_3V3 3,20,25,27 EM_A2 3,20,25,27 EM_A1 3,20,25,27 EM_WE R116 10K VCC_3V3 3 R367 10K VCC_3V3 R376 0 0 3 1 2 3 4 5 6 NAND_RB 7 8 9 10 11 12 0 13 14 15 16 17 18 19 20 21 22 23 24 NC.1 NC.2 NC.3 NC.4 NC.5 R/B2n R/Bn RE CE CE2 NC.11 VCC.1 VSS.1 NC.14 NC.15 CLE ALE WE WP NC.20 NC.21 NC.22 NC.23 NC.
A B C D 20 ONENAND_CE 5 3,25 EM_CLK 23 ONENAND_RST 3,25 EM_ADV 23 ONENAND_INT 3,25,26 EM_WAIT 3,20,25,26 EM_WE 3,20,25,26 EM_OE R375 10K VCC_3V3 3,25 EM_BA0 3,20,25 EM_A13 3,20,25 EM_A12 3,20,25 EM_A11 3,20,25 EM_A10 3,20,25 EM_A9 3,20,25 EM_A8 3,25 EM_A7 3,25 EM_A6 3,25 EM_A5 3,25 EM_A4 3,25 EM_A3 3,20,25,26 EM_A2 3,20,25,26 EM_A1 3,25 EM_A0 3,25 EM_BA1 R390 10K R377 10K R380 10K R364 10K R392 R481 10K 10K EM_BA0 EM_A13 EM_A12 EM_A11 EM_A10 EM_A9 EM_A8 EM_A7 EM_A6 EM_A5 EM_A4 EM_A3 E
A B C D 5 9,20,32,34,35,36,37,39,40,44 I2C_SCLK 9,20,32,34,35,36,37,39,40,44 I2C_DATA 5 R514 I2C_SCLK 4 R513 I2C_DATA R266 VCC_3V3 9 SPI0_SDENA0 9 SPI0_SDI 4 0 0 10K 0.1uF C365 VCC_3V3 R267 10K VCC_3V3 U16 CS SO WP GND VCC HOLD SCK SI 8 7 6 5 6 5 8 A0 A1 A2 WP VSS 3 CAT24C256 SCL SDA VCC U29 AT25640AN-10SU-2.7 1 2 3 4 3 1 2 3 7 4 0.
A B C D 5 9 UART0_RXD 9 UART0_TXD C7 1uF 15 4 14 4 2 1 9 C6 10uF UART0_RXD + 11 C130 1uF VCC_3V3 UART0_TXD R1 10K 4 U3 3 V- V+ C2- C2+ INVALID R_IN T_OUT FORCEON FORCEOFF MAX3221CPWRG4 GND C1- C1+ EN R_OUT T_IN VCC 3 16 7 3 6 5 10 8 13 12 C127 1uF C4 1uF GND_E_RS232 C123 10pF L3 L2 C131 1uF 1uH 1uH R178 10K VCC_3V3 GND_E_RS232 C124 10pF R186 10K VCC_3V3 C119 10pF GND_E_RS232 C118 10pF GND_E_RS232 2 2 P1 GND_E_RS232 L41 1 510842-00
A B C 8 SD0_DATA0 8 SD0_DATA1 8 SD0_CLK 8 SD0_DATA2 8 SD0_DATA3 8 SD0_CMD 5 R309 51K R305 51K R312 51K 4 R288 NO-POP R294 51K VCC_3V3 R329 NO-POP R323 51K VCC_3V3 R335 NO-POP R333 51K 3 R66 51K VCC_3V3 SD_DATA0 SD_DATA1 SD_CLK 9 1 2 3 4 5 6 7 8 SD.DAT2 SD.DAT3 SD.CMD SD.VSS1 SD.VDD SD.CLK SD.VSS2 SD.DAT0 SD.DAT1 MS.CMD.BS MS.DATA1 MS.DATA0 MS.DATA2 MS.DATA3 MS.CLK J12 SCDB1C0101/B1A0102 .1uF 10uF SD_DATA2 SD_DATA3 SD_CMD C307 + C308 VCC_3V3 R69 0 2 2 MS.VSS2 MS.VCC MS.
A-32 A B C D 5 8 CONN_SD1_DATA0 8 CONN_SD1_DATA1 8 CONN_SD1_CLK 8 CONN_SD1_DATA2 8 CONN_SD1_DATA3 8 CONN_SD1_CMD 5 R313 51K R319 51K R67 51K 4 R285 NO-POP R297 NO-POP R289 51K VCC_3V3 R281 51K VCC_3V3 4 R310 NO-POP R307 51K 3 CONN_SD1_DATA0 CONN_SD1_DATA1 CONN_SD1_CLK CONN_SD1_DATA2 CONN_SD1_DATA3 CONN_SD1_CMD 3 10uF + C311 VCC_3V3 .
A B C 0 0 0 R338 R339 R340 9,20,28,34,35,36,37,39,40,44 I2C_SCLK 5 R101 75 DENC_GND 9,20,28,34,35,36,37,39,40,44 I2C_DATA 7 DAC_2_B/PB 7 DAC_1_G/Y 7 DAC_3_R/PR DENC_GND R100 75 2 PLANE LINK PL4 4 DENC_GND R108 1 R107 DENC_GND I2C_SCLK DENC_GND R345 0 R355 NO-POP I2C_DATA R97 0 R98 NO-POP DENC_GND C326 NO-POP DENC_GND C325 NO-POP VCC_DENC DENC_GND C336 NO-POP DENC_GND R99 75 U23 NC20 11 12 13 14 15 16 17 18 19 20 C353 27pF DENC_GND 27pF DENC_GND 3 I2
A B C D 22 22 21 21 5 CPLD_CCD-DATA03 CPLD_CCD-DATA02 CPLD_CCD-DATA01 CPLD_CCD-DATA00 34 CCD-DATA03 34 CCD-DATA02 34 CCD-DATA01 34 CCD-DATA00 35 35 35 35 35 35 35 35 HD_C7 HD_C6 HD_C5 HD_C4 HD_C3 HD_C2 HD_C1 HD_C0 CCD-DATA3 CCD-DATA2 CCD-DATA1 CCD-DATA0 35 HD_CLKIN 35 HD_Y7 35 HD_Y6 35 HD_Y5 35 HD_Y4 35 HD_Y3 35 HD_Y2 35 HD_Y1 35 HD_Y0 35 HD_VSYNC 35 HD_HSYNC 8 7 6 5 1 2 3 4 34 CCD-PCLK CCD-DATA15 CCD-DATA14 CCD-DATA13 CCD-DATA12 CCD-VSYNC CCD-HSYNC 34 34 34 34 34 34 34 34 CCD-DATA11 CCD-DA
A B C D GND_MTR GND_STB 5 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 J10A L74 BLM41P750SPT L53 3V3A_CCD AGND_IMAGER 4 BLM41P750SPT L71 AFE_3V3 33 CCD-DATA14 33 CCD-VSYNC 33 CCD-HSYNC 22 CCD-FIELD 22 CCD-WEN 33 CCD-PCLK GPIO_MD10 GPIO_MD9 GPIO_MD8 GPIO_MD7 5V_DC_J6 MOT-PWR VCC_3V3 L81 B1 B2
A B C HD_C0 HD_C1 HD_C2 HD_C3 HD_C4 HD_C5 HD_C6 HD_C7 33 33 33 33 33 33 33 33 0 R321 5 NO-POP 0 R317 0 0 R518 R322 R314 0 0 R517 22 R324 VCC_3V3 NO-POP R320 VCC_3V3 9,20,28,32,34,36,37,39,40,44 I2C_SCLK 9,20,28,32,34,36,37,39,40,44 I2C_DATA R282 72 70 76 77 73 74 75 71 80 28 38 37 36 35 34 33 32 31 30 29 RN29 RPACK8-22 B_TVP_CR_CB2 9 8 B_TVP_CR_CB3 10 7 B_TVP_CR_CB4 11 6 B_TVP_CR_CB5 12 5 B_TVP_CR_CB6 13 4 B_TVP_CR_CB7 14 3 B_TVP_CR_CB8 15 2 B_TVP_CR_CB9 16 1 HD_C0 HD_C1
A B C D 5 9,20,28,32,34,35,37,39,40,44 I2C_DATA 9,20,28,32,34,35,37,39,40,44 I2C_SCLK R65 R64 I2C_SCLK I2C_DATA 35 THS7353_CH3 35 THS7353_CH2 35 THS7353_CH1 TVP_AGND TVP_AGND 4 C222 22pF C223 22pF 100 100 4 I2C_SDA_7353 I2C_SCL_7353 TVP_AGND 1uF C208 11 12 13 14 15 16 17 18 19 20 3 VS+ 33uF 10 9 8 7 6 5 4 3 2 1 33uF C59 C84 0.
A B C D 0.1uF LUMA 6 1 L29 1 L25 VCC_DEC_1V8 VCC_DEC_1V8 DEC_GND 5 2 BLM41P750SPT 1.8VD_DDEC 2 BLM41P750SPT 1.8VA_DDEC C356 0.1uF 0.1uF C335 .1uF C322 C312 680pF C316 330pF 1 L30 VCC_DEC_3V3 1 L26 DEC_GND L69 2.7uH C344 3.3VA_DDEC DEC_GND 75 R105 .1uF DEC_GND R352 75 2 BLM41P750SPT 3.3VD_DDEC 2 BLM41P750SPT 330pF C349 4 C357 0.1uF 2 DEC_GND PLANE LINK PL5 ISOLATE GROUNDS AND CONNECT AT SINGLE LOCATION IN THE GROUND PLANE 0.1uF C320 NO-POP R354 3.
A B C D 5 5 R238 360 9 McBSP_DR 9 McBSP_FSR 9 McBSP_CLKR 0.1uF C180 R239 360 9 McBSP_DX 9 McBSP_FSX 9 McBSP_CLKX 0.
5 6 P3 GND_AIC L45 GND_AIC C125 .1uF R175 10K R172 330 HEADER 9X2 2 4 6 8 10 12 14 16 18 1 3 5 7 9 11 13 15 17 C120 .1uF GND_AIC VCC_3V3 R32 R27 R23 R19 R13 R11 R191 5.6K R180 5.6K C146 .1uF GND_AIC R174 330 JP1 5.6K 5.6K BLM21PG221SN1D L39 R190 R179 21 AIC3101_RESETn GND_AIC R173 47K 4 2 1 Mic In GND_AIC 3 P4 4 2 1 Line In 3 C141 .
A B C R0 R1 R2 R3 R4 R5 R6 R7 6 VDOUT_VSYNC 9 SPI1_SDI 5 33 R135 B0 B1 B2 B3 B4 B5 B6 B7 BAT_VIN SPI1_SDI SPI1_CLK VDOUT_VCLK COUT0 COUT1 COUT2 COUT3 COUT4 6 VDOUT_VCLK 6 VDOUT_HSYNC BAT_VIN 33 33 R134 R132 9 SPI1_SDENA0 9 SPI1_SDO 9 SPI1_SCLK BLM41P750SPT L79 R1_GIO33 R1_GIO33 VDOUT_FIELD YOUT3 YOUT4 YOUT5 YOUT6 YOUT7 VCC_5V 23 G1_GIO30 23 R0_GIO32 23 R1_GIO33 G0 G1 G2 G3 G4 G5 G6 G7 R137 R138 R140 R142 4 SPI1_SDENA0 G1_GIO30 COUT5 COUT6 COUT7 YOUT0 YOUT1 YOUT2 33 33 33 33
A B C D 5 7 TV_OUT 23 GIO_DILC_VBUS_DET 23 GIO_DILC_DRV_VBUS1 23 GIO_DILC_CHG_CTL 23 GIO_DILC_AVJDET 23 SPI2_SDI_DILC 23 SPI2_SDO_DILC 23 SPI2_SCLK_DILC 23 GIO_DILC_CAM_PWR_DET 23 GIO_DILC_DOCK_DET AVJDET OP_SERIAL SB Q5 2 220 220 220 R458 R457 R456 R452 3.3K Q4 DTC114EUA R444 100K VCC_3V3 4 2 10K R445 R453 0 CAM_PWR PWR_VIN PWR_VIN 2 AVJ_DET DTC114EUA R446 100K R451 3.3K DTC114EUA VCC_3V3 R450 3.
A B C D 21 SEL_ENET_IO0 21 SEL_ENET_IO1 5 5 R47 CPU.TXCLK CPU.TXD0 CPU.TXD1 CPU.TXD2 CPU.TXD3 CPU.TX_EN 360 R236 9 CPU.COL 9 CPU.CRS 9 CPU.RXD0 9 CPU.RXD1 9 CPU.RXD2 9 CPU.RXD3 9 CPU.RX_DV 9 CPU.RX_ER 9 CPU.RX_CLK SEL_ENET_IO0 SEL_ENET_IO1 9 CPU.MDIO 9 CPU.
A B C D EPHY.TXCLK EPHY.TXD0 EPHY.TXD1 EPHY.TXD2 EPHY.TXD3 21 ENET_RESETn 42 EPHY.MDIO 42 EPHY.MDC 42 EPHY.RX_CLK 42 EPHY.COL 42 EPHY.CRS 42 EPHY.RXD0 42 EPHY.RXD1 42 EPHY.RXD2 42 EPHY.RXD3 42 EPHY.RX_DV 42 EPHY.RX_ER 42 EPHY.TX_EN 42 42 42 42 42 5 RN25 1 2 3 4 5 6 7 8 R202 NO-POP 16 15 14 13 12 11 10 9 TP7 TP-30 1.5K R212 VCC_3V3 R224 10K RPACK8-33 R201 NO-POP R223 10K 10K 10K R217 R16 R197 10K 4 R214 R15 R208 R21 R20 R216 VCC_3V3 EPHY.
A B C D TSOP34840 U1 21 MSP430_INT VCC_3V3 VCC_5V 2 1 3 R151 100 + R176 10K VCC_3V3 TPS79301-DBV VIN VOUT EN FB GND NR U36 R161 10K 5 9,20,28,32,34,35,36,37,39,40 I2C_DATA + 22 MP430_IO2 22 MP430_IO1 1 1 R512 4 0 0 R507 7 MP430_IO5 5 4 3 2 1 6 MP430_IO1 MP430_IO0 C126 0.1uF MP430_IO2 1 C121 10uF 6.3V 1 4 MSP430_3V3 MSP430_3V3 TP61 TEST POINT R187 30.1K R185 51K TP60 TEST POINT TP6 TEST POINT TP55 TEST POINT VCC_3V3 C1 10uF 6.
A-46 A B C D KEY_B1 KEY_B2 KEY_B3 3 3 KEY_B0 3 3 5 0 0 R437 R449 5 0 0 R430 R419 C412 100pF C409 100pF C405 100pF C386 100pF SW6 B B1 SW10 B B1 B B1 SW18 B B1 PUSHBUTTON SW A A1 PUSHBUTTON SW A A1 SW14 PUSHBUTTON SW A A1 PUSHBUTTON SW A A1 R443 1.5K R428 1.5K R417 1.5K R407 1.5K 4 4 SW7 B B1 SW11 B B1 B B1 SW19 B B1 C378 100pF R406 15K VCC_3V3 PUSHBUTTON SW A A1 PUSHBUTTON SW A A1 SW15 PUSHBUTTON SW A A1 PUSHBUTTON SW A A1 R442 1.
A B C D 5 5 LED1 LED2 LED3 LED4 LED5 LED6 LED7 23 23 23 22 22 22 22 A A1 LED0 23 B B1 PUSHBUTTON SW SW3 33 4 R221 LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 4 1uF C154 R213 10K VCC_3V3 LED LED R219 DS3 R387 330 DS2 R388 330 VCC_3V3 3 LED 0 R386 330 DS4 3 LED DS5 LED DS6 R384 330 PB_SWITCH 21 R385 330 LED DS7 R383 330 2 2 LED DS8 R382 330 Date: Size:B DWG NO SWITCHES 1 Sheet 46 o f DM368 Evaluation Module DM365 Evaluation Module SPECTRUM DIGITAL
A B 5 L16 BLM41P750SPT VIN_MAIN PL1 2 TEST POINT 4 1 TPS65510_AGND PLANE LINK 1 4.7uH TPS65510_PGND TP10 C183 2.2uF L13 C182 2.2uF R33 C32 PL2 2 1 2 3 4 R29 130K C24 2.2uF VO_BT SW PGND AGND TPS65510_PGND PLANE LINK 1 R30 0 TPS65510_AGND 392K 27pF 3 U9 R24 12 11 10 9 TPS65510 VR0 VOUT VO1R8 VO1R2 R28 75K 17 16 15 14 13 PWRPAD VBAT FB FBG VBK V_CTRL PWMON CS XRESET 5 6 7 8 Vvo_bt = 1 + ( R33/R29_R28) *1.
A B C D 1 2 3 TP65 TEST POINT + VCC6_IN VCC5_IN 1 1 10K + C22 22uF 4.7uH + 5 + C39 22uF BL_6V8 + BL_6V8_RTN D + C29 33uF R231 40.2K R232 560K GND_PCTL C162 22uF 2 4 MBR0530T1 + L12 R230 R34 D3 C155 10uF L10 R35 22pF C175 R36 0 4 15uH 15uH 0 15uH + 100K 680K D5 475K R48 100K 25 26 27 28 29 30 31 32 33 34 35 36 0.1uF R237 10 221K PGND3 SW8LD LL8 SW8HD PS FB8 FBG7/8 B-ADJ FBC CIN FBV SW7 GND_PCTL C37 10uF L15 + C50 22uF R51 82.5K 3 4.
A B C D 5 23 ENABLE_LCD_3V3 VCC_5V R402 10K BLM41P750SPT L33 21 ENABLE_LCD_15V R143 10K C375 0.001uF C103 2.2uF 4 + VCC_5V 4 C114 10uF 5 7 4 1 2 C408 47nF EN SS BIAS IN1 IN2 U31 R144 GND FB PG 6 8 3 10 9 TPS74701 0 VOUT2 VOUT1 PP1 4 3 7 6 2 GND SS FSW EN VIN U34 3 PWRPAD 3 11 A-50 11 5 R121 4.99K R127 15.8K PGND FB OUT L SW TPS61080 R432 L35 100 11.205 ) 10uF C104 -> 560K 2 R427 49.9K 1% R139 560K 1% BLM41P750SPT L32 R2 R1 4.
A B C CPU_VCC_3V3 CPU_VCC_3V3 TP57 TP-60 TP56 TP-60 5 1K 1K R491 R489 10K R488 10K R487 G G BSS138 Q8 R492 10K VCC_5V BSS138 Q7 R490 10K VCC_5V D S D S VCC_5V VCC_5V 4 4 R408 NO-POP R409 NO-POP C106 10uF C105 10uF 1 2 7 8 13 14 9 10 11 12 3 4 5 6 TPS767D301 NC.1 NC.2 NC.7 NC.8 NC.13 NC.14 2GND 2EN 2IN_1 2IN_2 1GND 1EN 1IN_1 1IN_2 U30 3 3 1 NO-POP L87 1RESET NC.15 NC.16 NC.20 NC.21 NC.26 NC.
A B C D 5 14,48 PWCTR_OUT1 TP70 TP-60 1K R502 G 4 NO-POP R497 4 BSS138 Q9 R504 10K VCC_5V TP69 TP-60 D VCC_5V VCC_5V R511 NO-POP R510 10K C429 10uF C428 10uF 3 3 1 2 7 8 13 14 9 10 11 12 3 4 5 6 TPS767D301 NC.1 NC.2 NC.7 NC.8 NC.13 NC.14 2GND 2EN 2IN_1 2IN_2 1GND 1EN 1IN_1 1IN_2 U42 1RESET NC.15 NC.16 NC.20 NC.21 NC.26 NC.
A TP52 TP-60 GND Test Points TP2 TP-60 TP51 TP41 TP-60 TP-60 D1 SMCJ6A 4 R199 2 GREEN DS1 R189 220 TP5 TP-30 + VCC_5V C15 47uF 3 2 SPECTRUM DIGITAL INCORPORATED 1 52 o f Revision: A D DWG NO Size:B Monday, January 10, 2011 1 510842-0001 POWER INPUT Page Contents: Date: DM368 Evaluation Module Title: Sheet 52 A B TP1 TP-60 F1 F_4.0A 2 B TP40 TP-60 NO-POP 1 3 C 5 CENTER SHUNT SLEEVE 2.
A-54 3 A 4 3 2 52 o f Revision: E D Size:B Monday, January 10, 2011 1 510842-0001 Revision Information DWG NO Page Contents: Date: DM368 Evaluation Module Title: Sheet 52 A B SPECTRUM DIGITAL INCORPORATED 1 B 5 2 C REVISION E is initial DM368 release.
Appendix B Mechanical Information This appendix contains the mechanical information about the DM368 EVM produced by Spectrum Digital.
THIS DRAWING IS NOT TO SCALE Spectrum Digital, Inc B-2 DM368 EVM Technical Reference
Printed in U.S.A.
