Reference Manual DOC. REV.
WWW.VERSALOGIC.COM 12100 SW Tualatin Road Tualatin, OR 97062-7341 (503) 747-2261 Fax (971) 224-4708 Copyright © 2013 VersaLogic Corp. All rights reserved. Notice: Although every effort has been made to ensure this document is error-free, VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose.
Product Revision Notes Revsion 1.00 – Commercial release. Support The Iguana support page, at http://www.versalogic.com/private/iguanasupport.
Contents Introduction ................................................................................................................... 1 Description.......................................................................................................................... 1 Features and Construction ..................................................................................... 1 Technical Specifications ................................................................................................
Contents Power Requirements ............................................................................................ 22 Power Delivery Considerations ........................................................................... 23 Lithium Battery.................................................................................................... 23 CPU................................................................................................................................... 24 System RAM...........
Contents Analog Input Using the SPI Interface .................................................................. 47 Analog Output .................................................................................................................. 49 Counter / Timers ............................................................................................................... 50 SPX ...............................................................................................................................
Introduction 1 Description FEATURES AND CONSTRUCTION The Iguana (VL-EPIC-25) is a feature-packed single board computer (SBC). It is designed for OEM control projects requiring compact size, high reliability, and longevity (product lifespan). Its features include: Intel Atom D425 Single Core or D525 Dual Core processor with ICH8M I/O hub Up to 2GB of DDR3 via a single SODIMM Dual Gigabit Ethernet PC/104-Plus expansion Eight USB 1.1/2.
Introduction Technical Specifications Specifications are typical at 25°C with +5V supply unless otherwise noted. Specifications are subject to change without notification. Board Size: Serial Ports 0-1: 4.5" x 6.5" (EPIC standard) RS-232/422/485, 16C550 compatible, 460 Kbps max.
Introduction Block Diagram Regulators Includes Power Mgt & Sequencing Logic Power Input Key: LVDS 18-bit LVDS Panel DDR3 Intel Atom Processor D425 (1 core) D525 (2 core) RGB VGA On-Board DDR3 SO-DIMM SMB CK505 Clock Generation SMB 4xDMI Gen 1 (FSB) X N/C X N/C Conn. Mag PCIe x1 [4,5] SATA 0 GPIO SATA1 Connector SATA 1 USB 8 USB 9 Intel 82801HM I/O Controller (ICH8M) PCIe x1 [1] Ethernet 0 GigE MAC/PHY Mag PC/104-Plus (PCI) PCIe Mini Card or mSATA SMB USB 2.
Introduction Thermal Considerations CPU DIE TEMPERATURE The CPU die temperature is affected by numerous conditions, such as CPU utilization, CPU speed, ambient air temperature, air flow, thermal effects of adjacent circuit boards, external heat sources, and many others. The CPU is protected from over-temperature conditions by two mechanisms. The CPU will automatically slow down by 50% whenever its die temperature exceeds +100°C.
Introduction RoHS Compliance The Iguana is RoHS-compliant. ABOUT ROHS In 2003, the European Union issued Directive 2002/95/EC regarding the Restriction of the use of certain Hazardous Substances (RoHS) in electrical and electronic equipment.
Introduction HANDLING CARE Warning! Care must be taken when handling the board not to touch the exposed circuitry with your fingers. Though it will not damage the circuitry, it is possible that small amounts of oil or perspiration on the skin could have enough conductivity to cause the Real Time Clock to become corrupted through careless handling. Technical Support If you are unable to solve a problem after reading this manual, please visit the Iguana product support Web page below.
Introduction Non-warranty Repair All approved non-warranty repairs are subject to diagnosis and labor charges, parts charges, and return shipping fees. Please specify the shipping method you prefer and provide a purchase order number for invoicing the repair. Note: VL-EPIC-25 Reference Manual Please mark the RMA number clearly on the outside of the box before returning.
Configuration and Setup 2 Initial Configuration The following components are recommended for a typical development system with the Iguana: ATX power supply DDR3 DRAM module USB keyboard and mouse SATA hard drive USB CD-ROM drive LVDS or VGA display The following VersaLogic cables are recommended: VL-CBR-2022 – Power adapter cable VL-CBR-5013 – Paddleboard VL-CBR-0701 – SATA data cable LVDS or VGA video adapter cable You will also need an operating system (OS) installation CD-ROM.
Configuration and Setup VL-CBR-5013B USB Keyboard and USB Mouse J4 J1 J7 VL-CBR-5013A J19 USB CDROM Drive J16 J17 J11 J12 IGUANA VL-EPIC-25 SATA Hard Drive VL-CBR-0401 J1 VL-CBR-2022 J2 J29 J3 SVGA or LVDS OS Installation CD-ROM VL-CBR-0701 ATX Power Supply VL-CBR-2010 or VL-CBR-2011 SVGA or LVDS VL-CBR-1201 Figure 1. Typical Start-up Configuration 1. Install Memory Insert a DDR3 DRAM module into SO-DIMM socket J1 on the bottom of the board and latch it into place. 2.
Configuration and Setup Plug the VL-CBR-5013A cable into the user I/O connector (J19) on the Iguana and the VL-CBR-5013B paddleboard (the cable is shipped attached to the paddleboard). Plug a USB keyboard and mouse into USB sockets J1 or J7 of the paddleboard. Plug the SATA data cable VL-CBR-0701 into socket J11 or J12. Attach a hard drive to the cable. Attach the ATX SATA power cable (VL-CBR-0401) to the ATX power supply and the SATA hard drive.
Physical Details 3 Dimensions and Mounting IGUANA DIMENSIONS The VL-EPIC-25 complies with EPIC dimensional standards. Dimensions are given below to help with pre-production planning and layout. 6.096 5.596 5.496 2.596 2.446 0.000 4.128 4.328 3.375 -0.200 0.000 -0.200 Figure 2. Iguana Dimensions and Mounting Holes (Not to scale. All dimensions in inches.
Physical Details VL-CBR-5013 DIMENSIONS 5.50 5.10 1.57 1.17 1.95 1.24 0.065 Figure 3. VL-CBR-5013 Dimensions and Mounting Holes (Not to scale. All dimensions in inches.
Physical Details VL-CBR-4004 DIMENSIONS 2.87 0.25 0.25 2.38 0.70 J1 J2 J3 J4 + + 1.95 0.63 J5 + + J6 J7 J8 J9 0.62 0.06 0.40 Figure 4. VL-CBR-4004 Dimensions and Mounting Holes (Not to scale. All dimensions in inches.
Physical Details HARDWARE ASSEMBLY The Iguana uses PC/104 and PC/104-Plus connectors so that expansion modules can be added to the top of the stack. PC/104 (ISA) modules must not be positioned between the Iguana and any PC/104-Plus (PCI) modules on the stack. The entire assembly can sit on a table top or be secured to a base plate. When bolting the unit down, make sure to secure all eight standoffs (A and B) to the mounting surface to prevent circuit board flexing.
Physical Details External Connectors IGUANA CONNECTOR LOCATIONS – TOP J25 – Digital, Analog, Timers J19 – User I/O J27 - SPX J22 J20 Ethernet 1 Ethernet 0 J28 External Ethernet LED J18 eUSB J16 J17 J16 - USB0 J17 - USB1 J6 PCI J11 - SATA0 J12 - SATA1 CD J13 PCIe Mini Card or mSATA DCBA J11 J12 J7-J8 ISA BA J2 VGA Atom CPU ICH8M J29 Power J3 – LVDS Figure 6.
Physical Details IGUANA CONNECTOR LOCATIONS – BOTTOM J9 CompactFlash J1 SODIMM Figure 7.
Physical Details IGUANA CONNECTOR FUNCTIONS AND INTERFACE CABLES Table 1 provides information about the function, mating connectors, and transition cables for Iguana connectors. Page numbers indicate where a detailed pinout or further information is available. Table 1: Connector Functions and Interface Cables Connector1 J1 J2 J3 J6 J7, J8 J9 Mating Connector Function 204-pin SO-DIMM 1.5V (DDR3 RAM) DDR3 Socket SVGA Video Output FCI 89361-712LF or FCI 89947-712LF LVDS 20-pin, PanelMate 1.
Physical Details VL-CBR-5013 CONNECTOR LOCATIONS SP1 Speaker J4 Paddleboard Adapter J2 COM0 (Top) COM1 (Bottom) J1 USB3 (Top) USB4 (Bottom) J8 Ext. Pushbutton Controls J5 COM2 J7 J3 S1 S2 J6 USB1 (Top) Audio Power Reset COM3 USB2 In (Top) D1 (Bottom) Out (Bottom) Programmable LED (Top) Power LED (Bottom) Figure 8.
Physical Details VL-CBR-4004 CONNECTOR LOCATIONS J1 J2 5 1 5 J3 1 5 J4 1 5 1 40 39 2 1 J5 1 5 J6 1 5 1 J7 5 J8 1 5 J9 = Pin 1 Figure 9.
Physical Details Jumper Blocks JUMPERS AS-SHIPPED CONFIGURATION V3 V4 2 1 4 6 8 V3 V4 1 3 5 2 V5 7 V1 3 V5 1 2 3 4 V7 1 2 V1 3 2 V2 1 2 1 V7 V2 V6 V6 2 1 Figure 10.
Physical Details JUMPER SUMMARY Table 3: Jumper Summary Jumper Block Description As Shipped V1[1-2-3] Factory Use Only. Jumper may be installed or removed.
System Features 4 Power Supply POWER CONNECTORS Main power is applied to the Iguana through an EPIC-style 10-pin polarized connector at location J29. Warning! To prevent severe and possibly irreparable damage to the system, it is critical that the power connectors are wired correctly. Make sure to use both +5VDC pins and all ground pins to prevent excess voltage drop.
System Features POWER DELIVERY CONSIDERATIONS Using the VersaLogic approved power supply (VL-PS200-ATX) and power cable (VL-CBR2022) will ensure high quality power delivery to the board. Customers who design their own power delivery methods should take into consideration the guidelines below to ensure good power connections. Also, the specifications for typical operating current do not include any off-board power usage that may be fed through the VL-EPIC-25 power connector.
System Features Figure 11. Battery Life vs.
System Features System RAM The Iguana accepts one 204-pin DDR3 SO-DIMM memory module with the following characteristics: Size Voltage Type Up to 2GB (1GB or 2GB recommended) +1.5V DDR3, 800 MT/s (400 MHz clock) Clearing Non-volatile RAM (NVRAM) You can clear NVRAM and reset the BIOS settings to factory defaults by following the instructions below. 1. Power off the Iguana. 2. Install a jumper on V6[1-2]. 3. Power on the Iguana and wait 10 seconds or more. 4. Power off the Iguana. 5.
System Features CLEARING THE REAL-TIME CLOCK You can move the V3 jumper to position [2-3] for a minimum of two seconds to clear the RTC. When clearing the RTC: 1. Power off the Iguana. 2. Move the jumper from V3[1-2] to V3[2-3] and leave it for two or more seconds. 3. Return the jumper to V3[1-2]. (The board will not boot if the jumper is not returned to this position.) 4. Power on the Iguana. This procedure sets the RTC date to Sat 01/01/2011.
Interfaces and Connectors Expansion Buses Note 5 5 Some information in this section may change as the BIOS continues in development. PC/104-PLUS (PCI + ISA) AND PCI-104 (PCI ONLY) PC/104-Plus and PCI-104 modules can be secured directly to the top of the Iguana. Make sure to correctly configure the slot position jumpers on each PC/104-Plus module appropriately. PC/104 (ISA only) modules must not be positioned between the Iguana and any PC/104-Plus or PCI-104 modules in the stack.
Interfaces and Connectors PC/104 I/O SUPPORT The following I/O ranges are available on the ISA bus unless there is a device claiming the range on the LPC bus (COM and LPT ports). Be sure to configure the ISA I/O ranges and the onboard serial ports in BIOS setup to avoid conflicts with one another. (An OS will not allocate I/O in the legacy ISA range.
Interfaces and Connectors Ethernet Interface The Iguana features two on-board Intel 82574IT Gigabit Ethernet controllers. The controllers provide a standard IEEE 802.3 Ethernet interface for 1000Base-T, 100Base-TX, and 10Base-T applications. RJ45 connectors are located at locations J22 (Ethernet 1) and J20 (Ethernet 0). While these controllers are not NE2000-compatible, they are widely supported. Drivers are readily available to support a variety of operating systems.
Interfaces and Connectors STATUS LED Connector J28 provides an additional on-board Ethernet status LED interface. The +3.3V power supplied to this connector is protected by a 1 Amp fuse. Table 7: Ethernet Status LED Pinout J28 Pin Signal Name Function On-Board LED Equivalent 1 2 3 4 5 6 7 8 9 10 +3.3V YEL1 ORN1 GRN1 +3.
Interfaces and Connectors Serial Ports The Iguana features four on-board 16550-based serial communications channels located at standard PC I/O addresses. All serial ports can be operated in RS-232 4-wire, RS-422, or RS-485 modes. IRQ lines are chosen in BIOS setup. Each COM port can be independently enabled, disabled, or assigned a different I/O base address in BIOS setup. COM PORT CONFIGURATION Use the BIOS setup screens to select between RS-232 and RS-422/485 operating modes.
Interfaces and Connectors SERIAL PORT CONNECTORS The pinouts of the DB9M connectors apply to the serial connectors on the VersaLogic breakout board VL-CBR-5013. These connectors use IEC 61000-4-2-rated TVS components to help protect against ESD damage.
Interfaces and Connectors Flash Interfaces COMPACTFLASH Connector J9 provides a socket for a Type I or Type II CompactFlash (CF) module. The CF interface supports operation in DMA mode. Contact VersaLogic Sales to order CF modules that have been tested and qualified as bootable devices. After installing the OS on the CF, you may configure the module to be the first boot device, which will reduce boot time.
Interfaces and Connectors The VL-MPEs-F1E series of mSATA modules provide flash storage of 4 GB, 16 GB, or 32 GB. To secure a Mini Card or mSATA module to the on-board standoffs, use two M2.5 x 6mm pan head Philips nylon screws. These screws are available in quantities of 10 in the VL-HDW-108 hardware kit from VersaLogic.
Interfaces and Connectors J13 Pin PCIe Mini Card Signal Name PCIe Mini Card Function mSATA Signal Name mSATA Function 41 42 43 44 45 46 47 48 49 50 51 52 3.3VAUX LED_WWAN# GND LED_WLAN# NC LED_WPAN# NC 1.5V Reserved GND Reserved 3.3VAUX 3.3V auxiliary source Wireless WAN LED 2 mSATA Detect Wireless LAN LED Not connected Wireless PAN LED Not connected 1.5V power Reserved Ground Reserved 3.3V auxiliary source +3.3V Reserved GND/NC Reserved Vendor Reserved Vendor +1.5V DA/DSS GND GND +3.3V 3.
Interfaces and Connectors Video An on-board video controller integrated into the chipset provides high-performance video output for the Iguana. The controller supports dual, simultaneous, independent video output. The Iguana can also be operated without video attached (see Console Redirection). The Iguana supports two types of video output, SVGA and LVDS Flat Panel Display.
Interfaces and Connectors LVDS FLAT PANEL DISPLAY CONNECTOR The integrated LVDS Flat Panel Display in the VL-EPIC-25 is an ANSI/TIA/EIA-644-1995 specification-compliant interface. It can support up to 18 bits of RGB pixel data plus 3 bits of timing control (HSYNC/VSYNC/DE) on the 4 differential data output pairs. The LVDS clock frequency ranges from 25 MHz to 112 MHz. Iguana has one LVDS connector at location J3. BIOS setup provides several options for standard LVDS flat panel types.
Interfaces and Connectors Audio The audio interface on the Iguana is implemented using an Integrated Device Technology, Inc. 92HD87B1X5 Audio Codec. This interface is Intel High Definition Audio compatible. Drivers are available for most Windows-based and Linux operating systems. To obtain the most current versions, consult the Iguana product support page. The J19 main I/O connector provides the line-level stereo input and line-level stereo output connection points.
Interfaces and Connectors User I/O Connector The 50-pin user I/O connector (J19) incorporates the COM ports, four USB ports, programmable LED, power LED, pushbutton reset, power button, audio line in/out, and speaker interfaces. The table below illustrates the function of each pin.
Interfaces and Connectors Pushbutton Reset Connector J19 includes an input for a pushbutton reset switch. Shorting J19 pin 40 to ground causes the Iguana to reboot. This must be a mechanical switch or an open-collector or open-drain active switch with less than a 0.5V low-level input when the current is 1 mA. There must be no pull-up resistor on this signal. This connector uses IEC 61000-4-2-rated TVS components to help protect against ESD damage.
Interfaces and Connectors External Speaker Connector J19 includes a speaker output signal at pin 39. The VL-CBR-5013 breakout board provides a Piezo electric speaker. LEDs PROGRAMMABLE LED Connector J19 includes an output signal for a programmable LED. Connect the cathode of the LED to J19 pin 38; connect the anode to +5V. A 332Ω on-board resistor limits the current to 15 mA when the LED is shorted. A programmable LED is provided on the VL-CBR-5013 breakout board.
Interfaces and Connectors Digital I/O The 40-pin I/O connector (J25) incorporates 16 digital I/O lines. Table 17 shows the function of each pin. The digital I/O lines are controlled using the SPI registers. See "SPI Registers" for a complete description of the registers. The digital lines are grouped into two banks of 16-bit bi-directional ports. The direction of each 8-bit port is controlled by software. The digital I/O lines are powered up in the input mode.
Interfaces and Connectors Digital I/O Interrupt Generation Using the SPI Interface Digital I/O can be configured to issue hardware interrupts on the transition (high to low or low to high) of any digital I/O pin. IRQ assignment is made in SPI control register SPISTATUS. This IRQ is shared among all SPI devices connected to the Iguana (the ADC and DAC devices on the SPI interface do not have interrupts). Digital I/O chip interrupt configuration is achieved through I/O port register settings.
Interfaces and Connectors MOV MOV OUT MOV MOV OUT MOV MOV OUT MOV MOV OUT MOV MOV OUT CALL DX, CA8h AL, 26h DX, AL DX, CA9h AL, 30h DX, AL DX, CABh AL, 44h DX, AL DX, CACh AL, 0Ah DX, AL DX, CADh AL, 40h DX, AL BUSY ;SPICONTROL: SPI Mode 00, 24bit, SPI 6 ;SPISTATUS: 8MHz, no IRQ, left-shift ;SPIDATA1: mirror and open-drain interrupts ;SPIDATA2: MCP23S17 IOCON register address 0Ah ;SPIDATA3: MCP23S17 write command ;Poll busy flag to wait for SPI transaction ;Configure MCP23S17 register IODIRA for outputs
Interfaces and Connectors '================================ 'SPICONTROL1 Register '--------------------------'D7 CPOL = 0 SPI Clock Polarity (SCLK idles low) 'D6 CPHA = 0 SPI Clock Phase (Data read on rising edge) 'D5 SPILEN1 = 1 SPI Frame Length (24-Bit) 'D4 SPILEN0 = 0 " " " " 'D3 MAN_SS = 0 SPI Slave Select Mode (Automatic) 'D2 SS2 = 1 SPI Slave Select (On-Board DIO 0-15) 'D1 SS1 = 1 " " " " " 'D0 SS0 = 0 " " " " " OUT SPICONTROL1, &H26 'SPICONTROL2 Register '--------------------------'D7 IRQSEL1 = 0 IR
Interfaces and Connectors 'INITIALIZE DIRECTION OF DIO LINES D15-D8 AS INPUTS '================================================== 'Direction = All Inputs OUT SPIDATA1, &HFF 'MCP23S17 IODIRA Register Address OUT SPIDATA2, &H0 'MCP23S17 SPI Control Byte (Write) OUT SPIDATA3, &H40 WHILE (INP(SPISTATUS) AND &H1) = &H1: WEND 'Repeat until ESC key is pressed WHILE INKEY$ <> CHR$(27) 'READ DIO INPUT DATA FROM MCP23S17 '--------------------------------'MCP23S17 GPIOA Register Address OUT SPIDATA2, &H12 'MCP23S17 S
Interfaces and Connectors Analog Input The Iguana uses a multi-range, 12-bit Linear Technology LTC1857 A/D converter with eight single-ended input signals (even and odd analog channels, for example inputs 1 and 2, can also be combined as differential inputs).
Interfaces and Connectors Initiating an Analog Conversion Using the SPI Interface The following procedure can be used to initiate an analog conversion using the SPI interface. 1. Write 15h to the SPICONTROL register (I/O address CA8h) – This value configures the SPI port to select the on-board A/D converter, 16-bit frame length, low SCLK idle state, rising edge SCLK edge, and automatic slave select. 2.
Interfaces and Connectors Analog Output The Iguana uses a 12-bit Linear Technology LTC2634 D/A converter with four (4) single-ended output signals. The converter has 5 µs per-channel update rate with a 0 to 4.096V output voltage range. The Iguana D/A converter is controlled using the SPI registers. The D/A converter is accessed via SPI slave select 7 (writing 7h to the SS field in SPICONTROL). See "SPI Registers" for a complete description of the registers.
Interfaces and Connectors Counter / Timers The Iguana includes two uncommitted 8254 type counter/timer channels for general program use. External control signals for the two channels are available on connector J25.
Interfaces and Connectors SPX Up to four serial peripheral expansion (SPX) devices can be attached to the Iguana at connector J27 using the VL-CBR-1401 or VL-CBR-1402 cable. The SPX interface provides the standard serial peripheral interface (SPI) signals: SCLK, MISO, and MOSI, as well as four chip selects, SS0# to SS3#, and an interrupt input, SINT#. The +5V power provided to pins 1 and 14 of J27 is protected by a 1 Amp resettable fuse.
Interfaces and Connectors VERSALOGIC SPX EXPANSION MODULES VersaLogic offers a number of SPX modules that provide a variety of standard functions, such as analog input, digital I/O, CANbus controller, and others. These are small boards (1.2” x 3.78”) that can mount on the PC/104 stack, using standard standoffs, or up to two feet away from the baseboard. For more information, contact VersaLogic at info@VersaLogic.com.
Interfaces and Connectors SPI REGISTERS A set of control and data registers are available for SPI transactions. The following tables describe the SPI control registers (SPICONTROL and SPISTATUS) and data registers (SPIDATA3-0). SPICONTROL (READ/WRITE) CA8h D7 D6 D5 D4 D3 D2 D1 D0 CPOL CPHA SPILEN1 SPILEN0 MAN_SS SS2 SS1 SS0 Table 22: SPI Control Register 1 Bit Assignments Bit Mnemonic D7 CPOL SPI Clock Polarity – Sets the SCLK idle state.
Interfaces and Connectors SPISTATUS (READ/WRITE) CA9h D7 D6 D5 D4 IRQSEL1 IRQSEL0 SPICLK1 SPICLK0 D3 D2 HW_IRQ_EN LSBIT_1ST D1 D0 HW_INT BUSY Table 23: SPI Control Register 2 Bit assignments Bit Mnemonic D7-D6 IRQSEL D5-D4 SPICLK D3 HW_IRQ_E N D2 LSBIT_1ST D1 HW_INT D0 BUSY Description IRQ Select – These bits select which IRQ will be asserted when a hardware interrupt from a connected SPI device occurs. The HW_IRQ_EN bit must be set to enable SPI IRQ functionality.
Interfaces and Connectors SPIDATA0 (READ/WRITE) CAAh D7 D6 D5 D4 D3 D2 D1 MSbit D0 LSbit SPIDATA1 (READ/WRITE) CABh D7 D6 D5 D4 D3 D2 D1 MSbit D0 LSbit SPIDATA2 (READ/WRITE) CACh D7 D6 D5 D4 D3 D2 D1 MSbit D0 LSbit SPIDATA3 (READ/WRITE) CADh D7 D6 MSbit D5 D4 D3 D2 D1 D0 LSbit SPIDATA3 contains the most significant byte (MSB) of the SPI data word.
System Resources and Maps 6 Legacy Memory Map The lower 1 MB memory map of the Iguana is arranged as shown in the following table. Various blocks of memory space between A0000h and FFFFFh are shadowed.
Special Registers 7 PLED and Product Code Register PLEDPC (Read/Write) CA0h D7 D6 D5 D4 D3 D2 D1 D0 PLED PC6 PC5 PC4 PC3 PC2 PC1 PC0 Table 26: PLED and Product Code Register Bit Assignments Bit Mnemonic D7 PLED Light Emitting Diode — Controls the programmable LED on connector J7. 0 = Turns LED off 1 = Turns LED on D6-D0 PC Product Code — These bits are hard-coded to represent the product type. The Iguana always reads as 0000011. Other codes are reserved for future products.
Interfaces and Connectors PLD Revision and Type Register REVTYP (Read Only) CA1h D7 D6 D5 D4 D3 D2 D1 D0 PLD4 PLD3 PLD2 PLD1 PLD0 TEMP CUSTOM BETA This register is used to indicate the revision level of the Iguana. Table 27: Revision and Type Register Bit Assignments Bit Mnemonic D7-D3 PLD D2 Reserved This bit is reserved. D1 CUSTOM PLD Class — This bit indicates whether the PLD code is standard or customized. 0 = Standard PLD code 1 = Custom PLD code This bit is read-only.
Special Registers BIOS and Jumper Status Register BIOSJSR (Read/Write) CA2h D7 D6 D5 D4 D3 D2 D1 D0 BIOS_JMP BIOS_OR BIOS_SEL Reserved Reserved Reserved Reserved GPI_JMP Table 28: Special Control Register Bit Assignments Bit Mnemonic D7 BIOS_JMP D6 BIOS_OR D5 BIOS_SEL D4-D2 D1 Reserved GPI_JMP D0 Reserved VL-EPIC-25 Reference Manual Description System BIOS Selector Jumper Status — Indicates the status of the system BIOS selector jumper at V5[1-2].
Appendix A – References CPU Intel Atom D425/D525 Dual Core Intel Atom Datasheet Vol. 1 and Vol.
Appendix B – Custom Programming B PLD Interrupts The PLD can generate interrupts for the internal 8254 timers and the external SPI interrupt (which includes the DIO device interrupt). The SPI interrupt settings are discussed in the section on “SPX Expansion Bus.” This section covers the interrupt settings for the 8254 timers. INTERRUPT CONTROL REGISTER This register enables interrupts.
Special Registers INTERRUPT STATUS REGISTER This register is used for reading the status of interrupts generated by the PLD. IRQSTAT (Read-Status/Write-Clear) CA4h D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Reserved Reserved ISTAT_TC5 ISTAT_TC4 ISTAT_TC3 Table 30: Interrupt Status Register Bit Assignments Bit Mnemonic Description D7-D3 Reserved D2 ISTAT _TC5 These bits are reserved. Only write 0 to these bits and ignore all read values.
Special Registers 8254 Timer Control Register This register is used to set modes related to the inputs on the 8254 Timers. TIMCNTRL (Read/Write) CA5h D7 D6 D5 D4 D3 D2 D1 D0 TIM5GATE TIM4GATE TIM3GATE TM4MODE TM4SEL TM3SEL Reserved Reserved Table 31: 8254 Timer Control Register Bit Assignments Bit Mnemonic Description D7 TIM5GATE Sets the level on the Gate input for the 8254 Timer #5.
Special Registers The 32-bit cascade mode is set in TM4MODE in the Timer Control Register. There are also internal or external clock selections for the timers in this register using the external clocks ICTC3 and ICTC4 signals on the connector at J25. The internal clock is the PCI clock divided by 8 (33.33 MHz / 8 = 4.167 MHz). ICTC3 can only be used with Timer 3. ICTC4 can only be used with Timer 4.
