Datasheet
TLV320AIC3107
www.ti.com
SLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014
Table 23. Page 0 / Register 17: MIC3L/R to Left ADC Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7-D4 R/W 1111 MIC3L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3L to the left ADC PGA
mix
0000: Input level control gain = 0.0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3.0 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6.0 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9.0 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12.0 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3L is not connected to the left ADC PGA
D3-D0 R/W 1111 MIC3R Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3R to the left ADC PGA
mix
0000: Input level control gain = 0.0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3.0 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6.0 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9.0 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12.0 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3R is not connected to the left ADC PGA
Table 24. Page 0 / Register 18: MIC3L/R to Right ADC Control Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7–D4 R/W 1111 MIC3L Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3L to the right ADC
PGA mix
0000: Input level control gain = 0.0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3.0 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6.0 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9.0 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12.0 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3L is not connected to the right ADC PGA
D3–D0 R/W 1111 MIC3R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3R to the right ADC
PGA mix
0000: Input level control gain = 0.0 dB
0001: Input level control gain = –1.5 dB
0010: Input level control gain = –3.0 dB
0011: Input level control gain = –4.5 dB
0100: Input level control gain = –6.0 dB
0101: Input level control gain = –7.5 dB
0110: Input level control gain = –9.0 dB
0111: Input level control gain = –10.5 dB
1000: Input level control gain = –12.0 dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3R is not connected to right ADC PGA
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