Datasheet

AudioSerialBusInterface
PGA
0/+59.5dB
0.5dBsteps
ADC
+
DAC
L
Volume
Control
DIN
DOUT
BCLK
WCLK
DINL
DINR DOUTL DOUTR
ADC
PGA
0/+59.5dB
0.5dBsteps
+
DACR
Volume
Control
Effects
AGC
AGC
RecordPath
RecordPath
DAC
Powered
Down
DAC
Powered
Down
Effects
SW-D1
SW-D2
SW-D3
SW-D4
LeftChannel
AnalogInputs
RightChannel
AnalogInputs
TLV320AIC3107
www.ti.com SLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014
Device Functional Modes (continued)
10.4.2 Digital Audio Processing For Record Path
In applications where record only is selected, and DAC is powered down, the playback path signal processing
blocks can be used in the ADC record path. These filtering blocks can support high pass, low pass, band pass or
notch filtering. In this mode, the record only path has switches SW-D1 through SW-D4 closed, and reroutes the
ADC output data through the digital signal processing blocks. Since the DAC's Digital Signal Processing blocks
are being re-used, naturally the addresses of these digital filter coefficients are the same as for the DAC digital
processing and are located on Page 1, Registers 1-52. This record only mode is enabled by powering down both
DACs by writing to Page 0, Register 37, bits D7-D6 (D7=D6=”0”). Next, enable the digital filter pathway for the
ADC by writing a “1” to Page 0, Register 107, bit D3. (Note, this pathway is only enabled if both DACs are
powered down.) This record only path can be seen in Figure 33.
Figure 33. Record Only Mode With Digital Processing Path Enabled
10.5 Programming
10.5.1 I
2
C Control Mode
The TLV320AIC3107 supports the I
2
C control protocol using 7-bit addressing, and is capable of both standard
and fast modes. The TLV320AIC3107 responds to the I
2
C address of 001 1000. For I
2
C fast mode, note that the
minimum timing for each of t
HD-STA
, t
SU-STA
, and t
SU-STO
is 0.9 μs, as seen in Figure 34.
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