Datasheet

TLV320AIC3107
SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014 www.ti.com
10.3.7 Input Impedance and VCM Control
The TLV320AIC3107 includes several programmable settings to control analog input pins, particularly when they
are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put into a 3-
state condition, such that the input impedance seen looking into the device is extremely high. Note, however, that
the pins on the device do include protection diode circuits connected to AVDD and AVSS. Thus, if any voltage is
driven onto a pin approximately one diode drop (~0.6 V) above AVDD or one diode drop below AVSS, these
protection diodes will begin conducting current, resulting in an effective impedance that no longer appears as a
3-state condition.
Another programmable option for unselected analog inputs is to weakly hold them at the common-mode input
voltage of the ADC PGA (which is determined by an internal bandgap voltage reference). This is useful to keep
the ac-coupling capacitors connected to analog inputs biased up at a normal DC level, thus avoiding the need for
them to charge up suddenly when the input is changed from being unselected to selected for connection to an
ADC PGA. This option is controlled in Page-0/Reg-20 and 23. The user should ensure this option is disabled
when an input is selected for connection to an ADC PGA or selected for the analog input bypass path, since it
can corrupt the recorded input signal if left operational when an input is selected.
In most cases, the analog input pins on the TLV320AIC3107 should be ac-coupled to analog input sources, the
only exception to this generally being if an ADC is being used for DC voltage measurement. The ac-coupling
capacitor will cause a highpass filter pole to be inserted into the analog signal path, so the size of the capacitor
must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed
analog signal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies
with the setting of the input level control, starting at approximately 20 kΩ with an input level control setting of 0
dB, and increasing to approximately 80-kΩ when the input level control is set at –12 dB. For example, using a
0.1 μF ac-coupling capacitor at an analog input will result in a highpass filter pole of 80 Hz when the 0 dB input
level control setting is selected.
10.3.8 General Purpose I/O
TLV320AIC3107 has a dedicated pin for General Purpose IO. This pin can be used to read status of external
signals through register read when configured as General Purpose Input. When configured as General Purpose
Output , this pin can also drive logic high or low. Besides these standard GPIO functions, this pin can also be
used in a variety of ways such as output for internal clocks and interrupt signals. TLV320AIC3107 generates a
variety of interrupts of use to the host processor such interrupts on jack detection, button press, short circuit
detection and AGC noise detection. All these interrupts can be routed individually to the GPIO pin or can be
combined by a logical OR. In the event of a combined interrupt, the user can read an internal status register to
find the actual cause of interrupt. When configured as interrupt, TLV320AIC3107 also offers the flexibility of
generating a single pulse or a train of pulses till the interrupt status register is read by the user.
10.3.9 MICBIAS Generation
The TLV320AIC3107 includes a programmable microphone bias output voltage (MICBIAS), capable of providing
output voltages of 2.0 V or 2.5 V (both derived from the on-chip bandgap voltage) with 4-mA output current drive.
In addition, the MICBIAS may be programmed to be switched to AVDD directly through an on-chip switch, or it
can be powered down completely when not needed, for power savings. This function is controlled by register
programming in Page-0/Reg-25.
10.3.10 Class-D Speaker Driver
Differential Class-D speaker outputs are available on the SPOP and SPOM pins as shown in Figure 28. The
integrated Class-D speaker amplifier can drive a one Watt audio signal into a differential 8- Ω load. The plus input
to the Class-D amplifier is the same signal available at the left lineout LEFT_LOP pin. The minus input to the
Class-D amplifier is an internal signal that is sourced as shown in Figure 32. A register (73) is used to enable the
Class-D amp and set its gain control (0 dB to +18 dB). Following the gain control and before the outputs is a
fixed +6 dB gain. Note that there are many other gains available in the signal path leading up to the Class-D amp
so for best results the user must map the gains correctly.
The following initialization sequence must be written to the AIC3107 registers prior to enabling the class-D
amplifier:
register data:
1. 0x00 0x0D
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