Datasheet

Volume0dBto
+9dB,mute
Volume0dBto
+9dB,mute
VCM
Volume0dBto
+9dB,mute
HPLOUT
HPCOM
HPROUT
DAC_L2
LINE2L
LINE2R
PGA_L
DAC_L1
DAC_R1
VOLUME
CONTROLS,
MIXING
PGA_R
DAC_R2
LINE2L
LINE2R
PGA_L
DAC_L1
DAC_R1
VOLUME
CONTROLS,
MIXING
PGA_R
LINE2L
LINE2R
PGA_L
DAC_L1
DAC_R1
VOLUME
CONTROLS,
MIXING
PGA_R
TLV320AIC3107
www.ti.com SLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014
Figure 27. Architecture of the Output Stage Leading to the High Power Output Drivers
The high power output drivers include additional circuitry to avoid artifacts on the audio output during power-on
and power-off transient conditions. The user should first program the type of output configuration being used in
Page-0/Reg-14, to allow the device to select the optimal power-up scheme to avoid output artifacts. The power-
up delay time for the high power output drivers is also programmable over a wide range of time delays, from
instantaneous up to 4-sec, using Page-0/Reg-42.
When these output drivers are powered down, they can be placed into a variety of output conditions based on
register programming. If lowest power operation is desired, then the outputs can be placed into a 3-state
condition, and all power to the output stage is removed. However, this generally results in the output nodes
drifting to rest near the upper or lower analog supply, due to small leakage currents at the pins. This then results
in a longer delay requirement to avoid output artifacts during driver power-on. In order to reduce this required
power-on delay, the TLV320AIC3107 includes an option for the output pins of the drivers to be weakly driven to
the VCM level they would normally rest at when powered with no signal applied. This output VCM level is
determined by an internal bandgap voltage reference, and thus results in extra power dissipation when the
drivers are in powerdown. However, this option provides the fastest method for transitioning the drivers from
powerdown to full power operation without any output artifact introduced.
The device includes a further option that falls between the other two – while it requires less power drawn while
the output drivers are in powerdown, it also takes a slightly longer delay to power-up without artifact than if the
bandgap reference is kept alive. In this alternate mode, the powered-down output driver pin is weakly driven to a
voltage of approximately half the DRVDD1/2 supply level using an internal voltage divider. This voltage will not
match the actual VCM of a fully powered driver, but due to the output voltage being close to its final value, a
much shorter power-up delay time setting can be used and still avoid any audible output artifacts. These output
voltage options are controlled in Page-0/Reg-42.
The high power output drivers can also be programmed to power up first with the output level control in a highly
attenuated state, then the output driver will automatically slowly reduce the output attenuation to reach the
desired output level setting programmed. This capability is enabled by default but can be enabled in Page-0/Reg-
40.
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