Datasheet

TLV320AIC3107

SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014

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10.3 Feature Description

10.3.1 Hardware Reset

The TLV320AIC3107 requires a hardware reset after power-up for proper operation. After all power supplies are

at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not

performed, the TLV320AIC3107 may not respond properly to register reads/writes.

10.3.2 Digital Audio Data Serial Interface

Audio data is transferred between the host processor and the TLV320AIC3107 via the digital audio data serial

interface, or audio bus. The audio bus on this device is flexible, including left or right justified data options,

support for I

S or PCM protocols, programmable data length options, a TDM mode for multichannel operation,

flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple devices

within a system directly.

The audio bus of the TLV320AIC3107 can be configured for left or right justified, I

S, DSP, or TDM modes of

operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.

These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word

clock (WCLK or GPIO1) and bit clock (BCLK) can be independently configured in either Master or Slave mode,

for flexible connectivity to a wide variety of processors

The word clock (WCLK or GPIO1) is used to define the beginning of a frame, and may be programmed as either

a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC

and DAC sampling frequencies.

The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in Master

mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In

continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated,

so in general the number of bit clocks per frame will be two times the data width. For example, if data width is

chosen as 16-bits, then 32 bit clocks will be generated per frame. If the bit clock signal in master mode will be

used by a PLL in another device, it is recommended that the 16-bit or 32-bit data width selections be used.

These cases result in a low jitter bit clock signal being generated, having frequencies of 32×Fs or 64×Fs. In the

cases of 20-bit and 24-bit data width in master mode, the bit clocks generated in each frame will not all be of

equal period, due to the device not having a clean 40×Fs or 48×Fs clock signal readily available. The average

frequency of the bit clock signal is still accurate in these cases (being 40×Fs or 48×Fs), but the resulting clock

signal has higher jitter than in the 16-bit and 32-bit cases.

In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.

The TLV320AIC3107 further includes programmability to 3-state the DOUT line during all bit clocks when valid

data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the

audio data will begin, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to

use a single audio serial data bus.

When the audio serial data bus is powered down while configured in master mode, the pins associated with the

interface will be put into a 3-state output condition.

10.3.2.1 Right Justified Mode

In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling

edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding

the rising edge of the word clock.

Product Folder Links: TLV320AIC3107