Datasheet
Audio Serial Bus Interface
LINE 2 LP
PGA
0/
+59.5dB
0.5dB
Steps
Left
Channel
ADC
HPCOM
HPLOUT
Left
Channel
DAC
AGC
Bias/
Reference
HPROUT
RIGHT _LOP
LEFT _LOP
MIC 3R /LINE 2RM
LINE 2RP /LINE 2LM
LINE 1RP
MIC 3L/LINE 1 RM
MICDET /LINE 1LM
LINE 1 LP
Feedthrough Line Paths to Class AB Line Amplifiers,
Passive Switches to Line Outputs,
and Class-D Speaker Amplifiers
SPOP
Right
Channel
ADC
Right
Channel
DAC
PGA
0/
+59.5dB
0.5dB
Steps
AGC
SPOM
Audio CLK
Gen
GPIO 1
MCLK
SWINP
SWINM
I2C Serial
Control Bus
SWOUTP
SWOUTM
Analog
Signal
Input
MIX/MUX,
Switching,
and/or
Attenuation
Digital
Audio
Filtering,
Volume
Control,
Effects,
and
Processing
Output
Amplifiers
MIX/MUX,
Switching,
and
Gain/Atten
AVDD_ADC
AVSS_ADC
DIN
DOUT
DVDD
IOVDD
DVSS
BCLK
WCLK
DRVDD
DRVSS
AVDD_DAC
AVSS_DAC
MICBIAS
RESET
SCL
SDA
SPVSS
SPVDD
H
E
A
D
P
H
O
N
E
L
I
N
E
C
L
A
S
S
D
QFN
Only
TLV320AIC3107
www.ti.com
SLOS545D –NOVEMBER 2008–REVISED DECEMBER 2014
9 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
10 Detailed Description
10.1 Overview
The TLV320AIC3107 is a highly flexible, low power, stereo audio codec with extensive feature integration,
intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment
applications. Available in a 5x5mm 40-lead QFN, the product integrates a host of features to reduce cost, board
space, and power consumption in space-constrained, battery-powered, portable applications.
The TLV320AIC3107 consists of the following blocks:
• Stereo audio multi-bit delta-sigma DAC (8 kHz–96 kHz)
• Stereo audio multi-bit delta-sigma ADC (8 kHz–96 kHz)
• Programmable digital audio effects processing (3-D, bass, treble, mid-range, EQ, notch filter, de-emphasis)
• Seven audio inputs
• Three high-power audio output drivers (headphone drive capability)
• Two single-ended line output drivers
• Fully programmable PLL
• Headphone/headset jack detection with interrupt
• Differential Class-D speaker driver
Communication to the TLV320AIC3107 for control is via I
2
C. The I
2
C interface supports both standard and fast
communication modes.
10.2 Functional Block Diagram
Connect QFN thermal pad to DRVSS.
Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TLV320AIC3107