Datasheet

T0145-01
WCLK
BCLK
SDOUT
SDIN
t (DO-BCLK)
d
t (DO-WS)
d
t (WS)
d
t (DI)
S
t (DI)
h
TLV320AIC3107
SLOS545D –NOVEMBER 2008 –REVISED DECEMBER 2014 www.ti.com
Audio Data Serial Interface Timing Requirements
(1)(2)
(continued)
IOVDD = 1.1 V IOVDD = 3.3 V
UNIT
MIN MAX MIN MAX
I
2
S/LJF/RJF TIMING IN SLAVE MODE, SEE Figure 3
t
P
(BCLK) BCLK clock period ns
t
H
(BCLK) BCLK high period 70 35 ns
t
L
(BCLK) BCLK low period 70 35 ns
t
s
(WS) ADWS/WCLK setup time 10 6 ns
t
h
(WS) ADWS/WCLK hold time 10 6 ns
t
d
(DO-WS) ADWS/WCLK to DOUT delay time (for LJF Mode only) 25 35 ns
t
d
(DO-BCLK) BCLK to DOUT delay time 50 20 ns
t
s
(DI) DIN setup time 10 6 ns
t
h
(DI) DIN hold time 10 6 ns
t
r
Rise time 8 4 ns
t
f
Fall time 8 4 ns
DSP TIMING IN SLAVE MODE, SEE Figure 4
t
P
(BCLK) BCLK clock period ns
t
H
(BCLK) BCLK high period 70 35 ns
t
L
(BCLK) BCLK low period 70 35 ns
t
s
(WS) ADWS/WCLK setup time 10 8 ns
t
h
(WS) ADWS/WCLK hold time 10 8 ns
t
d
(DO-BCLK) BCLK to DOUT delay time 50 20 ns
t
s
(DI) DIN setup time 10 6 ns
t
h
(DI) DIN hold time 10 6 ns
t
r
Rise time 8 4 ns
t
f
Fall time 8 4 ns
Figure 1. I
2
S/LJF/RJF Timing in Master Mode
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