Corp. SpaceWire Router User Manual

Ref.:
UoD_SpW-10X_
UserManual
Issue:
3.4
SpW-10X
SpaceWire Router
User Manual
Date:
11
th
July 2008
Preliminary
115
9.4.4 External port control/status register bits.
The port control/status fields specific to the External port are described in Table 9-7.
Table 9-7 External Port Control/Status Fields
Bits Name Reset
Value
Description Read/Write
0 Error Active ‘0’ This bit is set to one when any of the error bits are set. R
1 Packet
Address
Error
‘0’ The packet address error bit is set when a packet is
received with an incorrect address. A packet address
error is also generated when an empty packet is input
to the external port.
R
2 Output port
timeout
error
‘0’ The output timeout error bit is set when the output port
has become blocked for a period of time.
R
3 Input Buffer
Empty
‘0’ The external port input buffer is empty.
Note: The input buffer writes data to the SpaceWire
router.
R
4 Input Buffer
Full
‘0’ The external port input buffer is full. R
5 Output
Buffer
Empty
‘0’ The external output port buffer is empty.
Note: The output buffer writes data to the external
device connected to the external port.
R
6 Output
Buffer Full
‘0’ The external output port buffer is full. R
23:5 Not used - - -
Note: The Error status bits are cleared by writing to the Error Active register, see section 9.5.4.
9.5 ROUTER CONTROL/STATUS REGISTERS
The router control/status registers are described below.
9.5.1 Network Discovery Register
The network discovery register address is 256 (0x0000 0100).
The network discovery register allows a network manager to determine the layout of the network by
reading the contents of the register. Its fields are shown in Figure 9-4 and described in Table 9-8.