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Atmel 8051 Microcontroller Family - Product Selection Guide

Max speed depends on Vcc voltage. Frequencies and Currents listed are for

Vcc= 5.0V & T=25c

**Low voltage operation = 2.7-6.0V Operation

For further information please contact Equinox Technologies UK Ltd on Tel: +44 (0) 1204 529000 Fax: +44 (0) 1204 535555 E-mail: sales@equinox-tech.com

Disclaimer: Whilst information is supplied in good faith, we are not liable for any errors or omissions. Please consult the relevant Atmel datasheet. E&OE

Key

SRAM - Static RAM

ISP - In-System Programmable

I/O - Input/Output

ADC - Analogue to Digital Convertor

SPI - Serial Peripheral Interface

PWM - Pulse Width Modulation

PAR - Parallel programming mode

FLASH - Reprogrammable Code Memory

EEPROM - Parallel programming mode

Farnell Order Code Equinox Order Code

111-776 EQ-8051-ST1 (UK)

302-2365 AVR-DV1 (UK)

302-2298 UISP-S4

111-715 UISP-LV4

111-806 MPW-PLUS (UK)

302-2328 BK-C51-1

302-2237 EQ-89S-ST1

121-058 PK51-2K

302-2262 PK51-8K-UPG

302-2225 SG-ALLWRITER

Device 89C1051 89C1051U 89C2051 89C4051 89C51 89C52 89C55 89S8252 89S53

ON-CHIP MEMORY

Flash (Bytes) 1K 1K 2K 4K 4K 8K 20K 8K 12K

EEPROM (Bytes) 0 0 0 0 0 0 0 2K 0

SRAM (Bytes) 64 64 128 128 128 256 256 256 256

In-System Programmable (ISP) NO NO NO NO NO NO NO YES YES

HARDWARE FEATURES

I/O Pins 15 15 3 5 32 32 20 20 32

Enhanced LED I/O Drivers YES YES YES YES NO NO NO NO NO

SPI Port NO NO NO NO NO NO NO YES YES

Full Duplex Serial UART NO YES YES YES YES YES YES YES YES

Watchdog Timer NO NO NO NO NO NO NO YES YES

Timer/Counters 122223333

Analogue Comparator 11111NONONONO

IDLE and Power Down modes YES YES YES YES YES YES YES YES YES

Dual Data Pointer NO NO NO NO NO NO NO YES YES

Interrupt sources 366668899

MISCELLANEOUS

On-chip RC Oscillator NO NO NO NO NO NO NO NO NO

Max External Clock Frequency 24MHz 24MHz 24MHz 24MHz 24MHz 24MHz 24MHz 24MHz 24MHz

VCC Voltage Range (V) 2.7-6.0 2.7-6.0 2.7-6.0 2.7-6.0 4.0-6.0 4.0-6.0 4.0-6.0 4.0-6.0 4.0-6.0

Brown-out protection NO NO NO YES NO NO NO NO NO

EQUINOX SUPPORT TOOLS

Micro-ISP Series III Programmer NO NO NO NO NO NO NO ISP only ISP onlyNO

Micro-ISP Series IV Programmer NO NO NO NO NO NO NO ISP only ISP only

Micro-ISP Series IV LV Programmer NO NO NO NO NO NO NO ISP only ISP only

Micro-Pro Device Programmer PAR PAR PAR PAR PAR PAR PAR PAR PAR

8051 Starter System PAR PAR PAR PAR NO NO NO ISP/PAR ISP/PAR

Equinox Guide to C & the 8051 - - - - - - - - -

EQ-89S-ST1 NO NO NO NO NO NO NO ISP only ISP only

PK51-2K YES YES YES NO NO NO NO NO NO

PK51-8K-UPG YES YES YES YES YES YES NO YES NO

AllWriter Universal Programmer NO NO NO NO YES YES YES YES NO

Summary of content (34 pages)

PAGE 1
Atmel 8051 Microcontroller Family - Product Selection Guide Device 89C1051 89C1051U 89C2051 89C4051 89C51 89C52 89C55 89S8252 89S53 1K 1K 2K 4K 4K 8K 20K 8K 12K ON-CHIP MEMORY Flash (Bytes) EEPROM (Bytes) 0 0 0 0 0 0 0 2K 0 SRAM (Bytes) 64 64 128 128 128 256 256 256 256 In-System Programmable (ISP) NO NO NO NO NO NO NO YES YES 15 15 YES 3 5 32 32 20 20 **Low voltage operation = 2.7-6.
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Atmel 8051 Microcontroller Family - Product Selection Guide Continued....
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Features • Compatible with MCS-51™ Products • 12K Bytes of In-System Reprogrammable Downloadable Flash Memory • • • • • • • • • • • • • • – SPI Serial Interface for Program Downloading – Endurance: 1,000 Write/Erase Cycles 4.
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Pin Configurations PDIP P1.4 (SS) P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) (MOSI) P1.5 (MISO) P1.6 (SCK) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.
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AT89S53 Block Diagram P0.0 - P0.7 P2.0 - P2.7 PORT 0 DRIVERS PORT 2 DRIVERS VCC GND RAM ADDR. REGISTER B REGISTER PORT 0 LATCH RAM PORT 2 LATCH FLASH PROGRAM ADDRESS REGISTER STACK POINTER ACC BUFFER TMP2 TMP1 PC INCREMENTER ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PROGRAM COUNTER PSW PSEN ALE/PROG EA / VPP TIMING AND CONTROL INSTRUCTION REGISTER DPTR RST WATCH DOG PORT 3 LATCH PORT 1 LATCH SPI PORT PROGRAM LOGIC OSC PORT 3 DRIVERS P3.0 - P3.7 PORT 1 DRIVERS P1.0 - P1.
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Pin Description Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured as the SPI slave port select, data input/output and shift clock input/output pins as shown in the following table. Port Pin Alternate Functions P1.0 T2 (external count input to Timer/Counter 2), clock-out Port Pin Alternate Functions P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P1.
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AT89S53 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip.
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User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Timer 2 Registers Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 9) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16 bit capture mode or 16-bit auto-reload mode.
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AT89S53 Dual Data Pointer Registers To facilitate accessing external data memory, two banks of 16 bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR WCON selects DP0 and DPS = 1 selects DP1. The user should always initalize the DPS bit to the appropriate value before accessing the respective Data Pointer register. Power Off Flag The Power Off Flag (POF) is located at bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during power up.
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Table 4. SPCR—SPI Control Register SPCR Address = D5H Bit Reset Value = 0000 01XXB SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 7 6 5 4 3 2 1 0 Symbol Function SPIE SPI Interrupt Enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE = 1 and ES = 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts. SPE SPI Enable. SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and P1.7.
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AT89S53 Table Table 6. SPDR—SPI Data Register SPDR Address = 86H Bit Reset Value = unchanged SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 7 6 5 4 3 2 1 0 Data Memory - RAM Programmable Watchdog Timer The AT89S53 implements 256 bytes of RAM. The upper 128 bytes of RAM occupy a parallel space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.
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Timer 0 and 1 Timer 0 and Timer 1 in the AT89S53 operate the same way as Timer 0 and Timer 1 in the AT89C51, AT89C52 and AT89C55. For further information, see the October 1995 Microcontroller Data Book, page 2-45, section titled, “Timer/Counters.” Table 8. Timer 2 Operating Modes RCLK + TCLK CP/RL2 TR2 0 0 1 16-bit Auto-Reload 0 1 1 16-bit Capture 1 X 1 Baud Rate Generator X X 0 (Off) Timer 2 Timer 2 is a 16 bit Timer/Counter that can operate as either a timer or an event counter.
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AT89S53 EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16 bit value in RCAP2H and RCAP2L. The values in RCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16 bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.
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Figure 3. Timer 2 Auto Reload Mode (DCEN = 1) Figure 4. Timer 2 in Baud Rate Generator Mode TIMER 1 OVERFLOW ÷2 "0" "1" NOTE: OSC. FREQ.
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AT89S53 Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 4.
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Programmable Clock Out UART A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 5. This pin, besides being a regular I/0 pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.
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AT89S53 the SPI port is deactivated and the MOSI/P1.5 pin can be used as an input. There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figures 8 and 9. clock output in the master mode but is the clock input in the slave mode.
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Figure 9. SPI Transfer Format with CPHA = 1 SCK CYCLE # (FOR REFERENCE) 1 2 3 4 5 6 7 8 SCK (CPOL=0) SCK (CPOL=1) MOSI (FROM MASTER) MISO (FROM SLAVE) * MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB SS (TO SLAVE) *Not defined but normally LSB of previously transmitted character Interrupts The AT89S53 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt.
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AT89S53 Figure 12. External Clock Drive Configuration Figure 11. Oscillator Connections Note: C1, C2 = 30 pF ± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators Oscillator Characteristics internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited.
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Program Memory Lock Bits The AT89S53 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated.
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AT89S53 8. Repeat steps 3 through 7 changing the address and data for the entire 12K-byte array or until the end of the object file is reached. 9. Power-off sequence: Set XTAL1 to “L”. Set RST and EA pins to “L”. Turn VCC power off. The AT89S53 is shipped with the Serial Programming Mode enabled. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 must be pulled to a logic low.
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Serial Programming Algorithm To program and verify the AT89S53 in the serial programming mode, the following sequence is recommended: 1. Power-up sequence: Apply power between VCC and GND pins. Set RST pin to “H”. If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 24 MHz clock to XTAL1 pin and wait for at least 10 milliseconds. 2. Enable serial programming by sending the Programming Enable serial instruction to pin MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.
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AT89S53 Flash Parallel Programming Modes P2.6 P2.7 P3.6 P3.7 Data I/O P0.7:0 Address P2.5:0 P1.7:0 12V H L L L X X 12V L H H H DIN ADDR 12V L L H H DOUT ADDR 12V H L H L DIN X Bit - 1 P0.7 = 0 X Bit - 2 P0.6 = 0 X Bit - 3 P0.5 = 0 X DOUT X Bit - 1 @P0.2 X Bit - 2 @P0.1 X Bit - 3 @P0.0 X Mode Serial Prog.
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Figure 14. Flash Serial Downloading Figure 13. Programming the Flash Memory +5V +4.0V to 6.0V AT89S53 A0 - A7 ADDR. 0000H/2FFFH AT89S53 VCC P1 VCC PGM DATA P0 P2.0 - P2.5 A8 - A13 P2.6 SEE FLASH PROGRAMMING MODES TABLE PROG ALE P2.7 P3.6 INSTRUCTION INPUT P1.5/MOSI DATA OUTPUT P1.6/MISO CLOCK IN P1.7/SCK P3.7 XTAL2 VPP EA 3-24 Mhz 3-24 Mhz XTAL1 GND VI H RST PSEN +5V AT89S53 ADDR. 0000H/2FFFH A0 - A7 A8 - A13 SEE FLASH PROGRAMMING MODES TABLE P1 VCC P2.0 - P2.5 P0 P2.
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AT89S53 Flash Programming and Verification Characteristics - Parallel Mode TA = 0°C to 70°C, VCC = 5.0V ± 10% Symbol Parameter Min Max Units VPP Programming Enable Voltage 11.5 12.5 V IPP Programming Enable Current 1.0 mA 1/tCLCL Oscillator Frequency 24 MHz tAVGL Address Setup to PROG Low 48tCLCL tGHAX Address Hold After PROG 48tCLCL tDVGL Data Setup to PROG Low 48tCLCL tGHDX Data Hold After PROG 48tCLCL tEHSH P2.
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Flash Programming and Verification Waveforms - Parallel Mode Serial Downloading Waveforms SERIAL CLOCK INPUT SCK/P1.7 7 6 5 4 3 2 1 0 SERIAL DATA INPUT MOSI/P1.5 MSB LSB MSB LSB SERIAL DATA OUTPUT MISO/P1.
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AT89S53 Absolute Maximum Ratings* Operating Temperature .................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage............................................. 6.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
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AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.
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AT89S53 External Program Memory Read Cycle External Data Memory Read Cycle 4-243
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External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Symbol Parameter VCC = 4.0V to 6.0V 1/tCLCL Oscillator Frequency tCLCL Clock Period tCHCX Min Max Units 0 24 MHz 41.
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AT89S53 Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for VCC = 4.0V to 6V and Load Capacitance = 80 pF. Symbol Parameter 12 MHz Oscillator Min Max Variable Oscillator Min Units Max tXLXL Serial Port Clock Cycle Time 1.
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Notes: 4-246 1. XTAL1 tied to GND for ICC (power down) 2.
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AT89S53 Ordering Information Speed (MHz) Power Supply Ordering Code Package 16 4.0V to 6.0V AT89S53-16AA AT89S53-16JA AT89S53-16PA 44A 44J 40P6 Automotive (-40°C to 105°C) 24 4.0V to 6.0V AT89S53-24AC AT89S53-24JC AT89S53-24PC 44A 44J 40P6 Commercial (0°C to 70°C) 4.0V to 6.0V AT89S53-24AI AT89S53-24JI AT89S53-24PI 44A 44J 40P6 Industrial (-40°C to 85°C) 4.5V to 5.
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4-248 AT89S53