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Atmel 8051 Microcontrollers

Hardware Manual

Summary of content (116 pages)

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Atmel 8051 Microcontrollers Hardware Manual
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Table of Contents Section 1 The 8051 Instruction Set....................................................................... 1-2 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 Program Status Word................................................................................1-2 Addressing Modes ....................................................................................1-3 Arithmetic Instructions...............................................................................
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Section 1 The 8051 Instruction Set The 8051 instruction set is optimized for 8-bit control applications. It provides a variety of fast addressing modes for accessing the internal RAM to facilitate byte operations on small data structures. The instruction set provides extensive support for one-bit variables as a separate data type, allowing direct bit manipulation in control and logic systems that require Boolean processing.
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The 8051 Instruction Set Table 1-1. PSW: Program Status Word Register (MSB) (LSB) CY AC F0 RS1 RS0 OV - P Symbol Position Name and Significance CY PSW.7 Carry flag AC PSW.6 Auxiliary Carry flag. (For BCD operations.) F0 PSW.5 Flag 0 (Available to the user for general purposes.) Register bank Select control bits 1 & 0. Set/cleared by software to determine working register bank (see Note). RS1 PSW.4 RS0 PSW.3 OV PSW.2 Overflow flag. - PSW.1 (reserved) PSW.0 Parity flag.
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The 8051 Instruction Set 1.2.3 Register Instructions The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-bit register specification within the opcode of the instruction. Instructions that access the registers this way are code efficient, since this mode eliminates an address byte. When the instruction is executed, one of the eight registers in the selected bank is accessed.
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The 8051 Instruction Set 1.3 Arithmetic Instructions The menu of arithmetic instructions is listed in Table 1-2. The table indicates the addressing modes that can be used with each instruction to access the operand. For example, the ADD A, instruction can be written as: ADD ADD ADD ADD A,7FH (direct addressing) A,@ R0(indirect addressing) A,R7 (register addressing) A,# 127(immediate constant) Table 1-2. A list of the Atmel 8051 Arithmetic Instructions.
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The 8051 Instruction Set The DA A instruction is for BCD arithmetic operations. In BCD arithmetic ADD and ADDC instructions should always be followed by a DA A operation, to ensure that the result is also in BCD. Note that DAA will not convert a binary number to BCD. The DA A operation produces a meaningful result only as the second step in the addition of two BCD bytes. 1.4 Logical Instructions Table 1-3 shows the list of logical instructions.
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The 8051 Instruction Set Note that Boolean operations can be performed on any byte in the internal Data Memory space without going through the Accumulator. The XRL , # data instruction, for example, offers a quick and easy way to invert port bits, as in XRL P1, #OFFH If the operation is in response to an interrupt, not using the Accumulator saves the time and effort to stack it in the service routine. The Rotate instructions (RL A, RLC A, etc.) shift the Accumulator 1 bit to the left or right.
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The 8051 Instruction Set This means the stack can go into the Upper 128, if they are implemented, but not into SFR space. Table 1-4.
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The 8051 Instruction Set Table 1-5.
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The 8051 Instruction Set repeated for location 2DH. The CJNE instruction (Compare and Jump if Not Equal) is a loop control that will be described later. The loop is executed from LOOP to CJNE for R1 = 2EH, 2DH, 2CH and 2BH. At that point the digit that was originally shifted out on the right has propagated to location 2AH. Since that location should be left with 0s, the lost digit is moved to the Accumulator. 1.
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The 8051 Instruction Set MOV A, ENTRY_NUMBER CALLTABLE The subroutine “TABLE” would look like this: TABLE:MOVC A, @A + PC RET The table itself immediately follows the RET (return) instruction in Program Memory. This type of table can have up to 255 entries, numbered 1 through 255. Number 0 cannot be used, because at the time the MOVC instruction is executed, the PC contains the address of the RET instruction. An entry numbered 0 would be the RET opcode itself. Table 1-8. Lookup Table Read Instructions 1.
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The 8051 Instruction Set In this example, FLAG is the name of any addressable bit in the lower 128 or SFR space. An I/O line (the LSB of Port 1, in the case) is set or cleared depending on whether the flag bit is 1 or 0. The Carry bit in the PSW is used as the single-bit Accumulator of the Boolean processor. Bit instructions that refer to the Carry bit as C assemble as Carry-specific instructions (CLR C, etc.).
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The 8051 Instruction Set Table 1-10. Addressing Modes addr 11 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K byte page of program memory as the first byte of the following instruction. rel Signed (two’s complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction. bit Direct Addressed bit in Internal Data RAM or Special Function Register. 1.
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The 8051 Instruction Set The RLA instruction converts the index number (0 through 4) to an even number on the range 0 through 8, because each entry in the jump table is 2 bytes long: JUMP_TABLE: AJMP CASE_0 AJMP CASE_1 AJMP CASE_2 AJMP CASE_3 AJMP CASE_4 Table 1-11 shows a single “CALL addr” instruction, but there are two of them -LCALL and ACALL -which differ in the format in which the subroutine address is given to the CPU.
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The 8051 Instruction Set * (end loop) DJNZ COUNTER, LOOP (continue) The CJNE instruction (Compare and Jump if Not Equal) can also be used for loop control as in Table 1-12. Two bytes are specified in the operand field of the instruction. The jump is executed only if the two bytes are not equal. In the example of Figure 12, the two bytes were the data in R1 and the constant 2AH. The initial data in R1 was 2EH.
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The 8051 Instruction Set 1.
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The 8051 Instruction Set Mnemonic Description Byte Oscillator Period ANL A,#data AND immediate data to Accumulator 2 12 ANL direct,A AND Accumulator to direct byte 2 12 ANL direct,#data AND immediate data to direct byte 3 24 ORL A,Rn OR register to Accumulator 1 12 ORL A,direct OR direct byte to Accumulator 2 12 ORL A,@Ri OR indirect RAM to Accumulator 1 12 ORL A,#data OR immediate data to Accumulator 2 12 ORL direct,A OR Accumulator to direct byte 2 12 ORL dire
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The 8051 Instruction Set Mnemonic Description Byte Oscillator Period MOV direct,#data Move immediate data to direct byte 3 24 MOV @Ri,A Move Accumulator to indirect RAM 1 12 MOV @Ri,direct Move direct byte to indirect RAM 2 24 MOV @Ri,#data Move immediate data to indirect RAM 2 12 MOV DPTR,#data16 Load Data Pointer with a 16-bit constant 3 24 MOVC A,@A+DPTR Move Code byte relative to DPTR to Acc 1 24 MOVC A,@A+PC Move Code byte relative to PC to Acc 1 24 MOVX A,@Ri
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The 8051 Instruction Set Mnemonic Description Byte Oscillator Period JB bit,rel Jump if direct Bit is set 3 24 JNB bit,rel Jump if direct Bit is Not set 3 24 JBC bit,rel Jump if direct Bit is set & clear bit 3 24 PROGRAM BRANCHING ACALL addr11 Absolute Subroutine Call 2 24 LCALL addr16 Long Subroutine Call 3 24 RET Return from Subroutine 1 24 RETI Return from 1 24 interrupt AJMP addr11 Absolute Jump 2 24 LJMP addr16 Long Jump 3 24 SJMP rel Short Jump (relat
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The 8051 Instruction Set 1.12 Instructions That Affect Flag Settings Table 1-13. Instructions that affect Flag Settings Instruction Flag Instruction Flag C OV AC C ADD X X X CLR C O ADDC X X X CPL C X SUBB X X X ANL C,bit X MUL O X ANL C,/bit X DIV O X ORL C,bit X DA X ORL C,/bit X RRC X MOV C,bit X RLC X CJNE X OV AC SETB C 1 Note: Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW or bits in the PSW) also affect flag settings.
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The 8051 Instruction Set 1.
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1-21 4316E–8051–01/07 MOVX A,@DPTR 1-2 MOVX @DPTR,A 1-2 Fx MOV DPTR,#imm16 3-2 9x Ex SJMP rel 2-2 8x POP dir 2-2 JNZ rel 2-2 7x Dx JZ rel 2-2 6x PUSH dir 2-2 JNC rel 2-2 5x Cx JC rel 2-2 4x ANL C,/bit 2-2,C JNB bit,rel 3-2 3x Bx JB bit,rel 3-2 2x ORL C,/bit 2-2,C JBC bit,rel 3-2 1x Ax NOP 1-1 Ox x0 ACALL addr11 2-2 AJMP addr11 2-2 ACALL addr11 2-2 AJMP addr11 2-2 ACALL addr11 2-2 AJMP addr11 2-2 ACALL addr11 2-2 AJMP addr11 2-2 ACALL addr11 2-2 AJMP addr11 2-2 AC
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INC R0 1-1 DEC R0 1-1 ADD A,R0 1-1,C,OV,AC ADDC A,R0 1-1,C,OV,AC ORL A,R0 1-1 ANL A,R0 1-1 XRL A,R0 1-1 MOV R0,#imm 2-1 MOV dir,R0 2-2 SUBB A,R0 1-1,C,OV,AC MOV R0,dir 2-2 CJNE R0,#imm,rel 3-2,C XCH A,R0 1-1 DJNZ R0,rel 2-2 MOV A,R0 1-1 MOVX R0,A 1-1 Ox 1x 2x 3x 4x 5x 6x 7x 8x 9x Ax Bx Cx Dx Ex Fx x8 Atmel 8051 Microcontrollers Hardware Manual MOVX R1,A 1-1 MOV A,R1 1-1 DJNZ R1,rel 2-2 XCH A,R1 1-1 CJNE R1,#imm,rel 3-2,C MOV R1,dir 2-2 SUBB A,R1 1-1,C,OV,AC MOV dir,R1 2-2 MOV R1,
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The 8051 Instruction Set 1.14 Instruction Definitions 1.14.1 ACALL addr11 Function: Absolute Call Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice.
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The 8051 Instruction Set 1.14.2 ADD A, Function: Add Description: ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred. OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6; otherwise, OV is cleared.
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The 8051 Instruction Set 1.14.3 ADDC A, Function: Add with Carry Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents, leaving the result in the Accumulator. The carry and auxiliary-carry flags are set respectively, if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.
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The 8051 Instruction Set 1.14.4 AJMPaddr11 Function: Absolute Jump Description: AJMP transfers program execution to the indicated address, which is formed at run-time by concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7 through 5, and the second byte of the instruction. The destination must therfore be within the same 2 K block of program memory as the first byte of the instruction following AJMP.
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The 8051 Instruction Set 1.14.5 ANL, Function: Logical-AND for byte variables Description: ANL performs the bitwise logical-AND operation between the variables indicated and stores the results in the destination variable. No flags are affected. The two operands allow six addressing mode combinations.
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The 8051 Instruction Set ANL A,#data Bytes: 2 Cycles: 1 Encoding: 0 1 Operation: ANL (A) ← (A) ANL 0 1 0 1 0 0 immediate data 1 0 0 1 0 direct address 0 0 1 1 direct address ∧ #data direct,A Bytes: 2 Cycles: 1 Encoding: 0 1 0 Operation: ANL (direct) ← (direct) ANL ∧ (A) direct,#data Bytes: 3 Cycles: 2 Encoding: 0 1 0 Operation: ANL (direct) ← (direct) 1.14.
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The 8051 Instruction Set ANL C,/bit Bytes: 2 Cycles: 2 Encoding: 1 0 Operation: ANL (C) ← (C) 1.14.7 1 ∧ 1 0 0 0 0 bit address (bit) CJNE ,, rel Function: Compare and Jump if Not Equal. Description: CJNE compares the magnitudes of the first two operands and branches if their values are not equal.
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The 8051 Instruction Set CJNE A,#data,rel Bytes: 3 Cycles: 2 Encoding: 1 0 1 1 0 1 0 0 immediate data rel. address r r r immediate data rel. address 1 1 i immediate data rel.
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The 8051 Instruction Set 1.14.8 CLR A Function: Clear Accumulator Description: CLR A clears the Accumulator (all bits set to 0). No flags are affected Example: The Accumulator contains 5CH (01011100B). The following instruction,CLR Aleaves the Accumulator set to 00H (00000000B). Bytes: 1 Cycles: 1 Encoding: 1 1 1 0 0 1 0 0 Operation: CLR (A) ← 0 1.14.9 CLR bit Function: Clear bit Description: CLR bit clears the indicated bit (reset to 0). No other flags are affected.
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The 8051 Instruction Set 1.14.10 CPL A Function: Complement Accumulator Description: CPLA logically complements each bit of the Accumulator (one’s complement). Bits which previously contained a 1 are changed to a 0 and vice-versa. No flags are affected. Example: The Accumulator contains 5CH (01011100B). The following instruction, CPL A leaves the Accumulator set to 0A3H (10100011B). Bytes: 1 Cycles: 1 Encoding: 1 Operation: CPL (A) ← 1.14.
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The 8051 Instruction Set 1.14.12 DA A Function: Decimal-adjust Accumulator for Addition Description: DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two variables (each in packed-BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition.
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The 8051 Instruction Set 1.14.13 DECbyte Function: Decrement Description: DEC byte decrements the variable indicated by 1. An original value of 00H underflows to 0FFH. No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Register 0 contains 7FH (01111111B).
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The 8051 Instruction Set 1.14.14 DIVAB Function: Divide Description: DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer in register B. The Accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags are cleared. Exception: if B had originally contained 00H, the values returned in the Accumulator and B-register are undefined and the overflow flag are set. The carry flag is cleared in any case.
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The 8051 Instruction Set 1.14.15 DJNZ, Function: Decrement and Jump if Not Zero Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00H underflows to 0FFH. No flags are affected.
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The 8051 Instruction Set 1.14.16 INC Function: Increment Description: INC increments the indicated variable by 1. An original value of 0FFH overflows to 00H. No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. Example: Register 0 contains 7EH (011111110B).
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The 8051 Instruction Set 1.14.17 INC DPTR Function: Increment Data Pointer Description: INC DPTR increments the 16-bit data pointer by 1. A 16-bit increment (modulo 216) is performed, and an overflow of the low-order byte of the data pointer (DPL) from 0FFH to 00H increments the high-order byte (DPH). No flags are affected. This is the only 16-bit register which can be incremented. Example: Registers DPH and DPL contain 12H and 0FEH, respectively.
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The 8051 Instruction Set 1.14.19 JBC bit,rel Function: Jump if Bit is set and Clear bit Description: If the indicated bit is one, JBC branches to the address indicated; otherwise, it proceeds with the next instruction. The bit will not be cleared if it is already a zero. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. No flags are affected.
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The 8051 Instruction Set 1.14.21 JMP @A+DPTR Function: Jump indirect Description: JMP @A+DPTR adds the eight-bit unsigned contents of the Accumulator with the 16-bit data pointer and loads the resulting sum to the program counter. This is the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 216): a carry-out from the low-order eight bits propagates through the higher-order bits. Neither the Accumulator nor the Data Pointer is altered. No flags are affected.
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The 8051 Instruction Set 1.14.23 JNC rel Function: Jump if Carry not set Description: If the carry flag is a 0, JNC branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signal relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The carry flag is not modified. Example: The carry flag is set.
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The 8051 Instruction Set 1.14.25 JZ rel Function: Jump if Accumulator Zero Description: If all bits of the Accumulator are 0, JZ branches to the address indicated; otherwise, it proceeds with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not modified. No flags are affected. Example: The Accumulator originally contains 01H.
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The 8051 Instruction Set 1.14.27 LJMPaddr16 Function: Long Jump Description: LJMP causes an unconditional branch to the indicated address, by loading the high-order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space. No flags are affected. Example: The label JMPADR is assigned to the instruction at program memory location 1234H.
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The 8051 Instruction Set *MOV A,direct Bytes: 2 Cycles: 1 Encoding: 1 1 1 0 0 1 0 1 direct address Operation: MOV (A) ← (direct) * MOV A,ACC is not a valid Instruction. MOV A,@Ri Bytes: 1 Cycles: 1 Encoding: 1 1 1 0 0 1 1 i 1 1 0 1 0 0 1 1 1 r r r 1 0 1 r r r direct addr.
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The 8051 Instruction Set MOV direct,A Bytes: 2 Cycles: 1 Encoding: 1 1 1 1 0 1 0 1 direct address 0 0 1 r r r direct address 0 0 1 0 1 dir. addr. (scr) 0 0 1 1 i direct addr. 1 0 1 0 1 direct address 1 0 1 1 i Operation: MOV (direct) ← (A) MOV direct,Rn Bytes: 2 Cycles: 2 Encoding: 1 0 Operation: MOV (direct) ← (Rn) MOV direct,direct Bytes: 3 Cycles: 2 Encoding: 1 0 0 dir. addr.
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The 8051 Instruction Set MOV @Ri,direct Bytes: 2 Cycles: 2 Encoding: 1 0 1 0 0 1 1 i direct addr. 1 0 1 1 i immediate data Operation: MOV ((Ri)) ← (direct) MOV @Ri,#data Bytes: 2 Cycles: 1 Encoding: 0 1 1 Operation: MOV ((Ri)) ← #data 1.14.29 MOV , Function: Move bit data Description: MOV , copies the Boolean variable indicated by the second operand into the location specified by the first operand.
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The 8051 Instruction Set 1.14.30 MOV DPTR,#data16 Function: Load Data Pointer with a 16-bit constant Description: MOV DPTR,#data16 loads the Data Pointer with the 16-bit constant indicated. The 16-bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the lower-order byte. No flags are affected. This is the only instruction which moves 16 bits of data at once.
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The 8051 Instruction Set MOVC A,@A+DPTR Bytes: 1 Cycles: 2 Encoding: 1 0 0 1 0 0 1 1 0 0 1 1 Operation: MOVC (A) ← ((A) + (DPTR)) MOVC A,@A+PC Bytes: 1 Cycles: 2 Encoding: 1 0 0 0 Operation: MOVC (PC) ← (PC) + 1 (A) ← ((A) + (PC)) 1.14.32 MOVX , Function: Move External Description: The MOVX instructions transfer data between the Accumulator and a byte of external data memory, which is why “X” is appended to MOV.
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The 8051 Instruction Set Operation: MOVX (A) ← ((Ri)) MOVX A,@DPTR Bytes: 1 Cycles: 2 Encoding: 1 1 1 0 0 0 0 0 1 1 0 0 1 i 1 1 0 0 0 0 Operation: MOVX (A) ← ((DPTR)) MOVX @Ri,A Bytes: 1 Cycles: 2 Encoding: 1 1 Operation: MOVX ((Ri)) ← (A) MOVX @DPTR,A Bytes: 1 Cycles: 2 Encoding: 1 1 Operation: MOVX (DPTR) ← (A) 1.14.33 MUL AB Function: Multiply Description: MUL AB multiplies the unsigned 8-bit integers in the Accumulator and register B.
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The 8051 Instruction Set 1.14.34 NOP Function: No Operation Description: Execution continues at the following instruction. Other than the PC, no registers or flags are affected. Example: A low-going output pulse on bit 7 of Port 2 must last exactly 5 cycles. A simple SETB/CLR sequence generates a one-cycle pulse, so four additional cycles must be inserted. This may be done (assuming no interrupts are enabled) with the following instruction sequence, CLR P2.7 NOP NOP NOP NOP SETB P2.
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The 8051 Instruction Set 1.14.35 ORL Function: Logical-OR for byte variables Description: ORL performs the bitwise logical-OR operation between the indicated variables, storing the results in the destination byte. No flags are affected. The two operands allow six addressing mode combinations.
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The 8051 Instruction Set ORL A,#data Bytes: 2 Cycles: 1 Encoding: 0 1 Operation: ORL (A) ← (A) ORL 0 0 0 1 0 0 immediate data 0 0 0 1 0 direct address 0 0 1 1 direct addr. ∨ #data direct,A Bytes: 2 Cycles: 1 Encoding: 0 1 0 Operation: ORL (direct) ← (direct) ORL ∨ (A) direct,#data Bytes: 3 Cycles: 2 Encoding: 0 1 0 Operation: ORL (direct) ← (direct) 1.14.
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The 8051 Instruction Set Cycles: 2 Encoding: 1 0 Operation: ORL (C) ← (C) 1-53 4316E–8051–01/07 1 0 0 0 0 0 bit address ∨ (bit) Atmel 8051 Microcontrollers Hardware Manual
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The 8051 Instruction Set 1.14.37 POP direct Function: Pop from stack. Description: The contents of the internal RAM location addressed by the Stack Pointer is read, and the Stack Pointer is decremented by one. The value read is then transferred to the directly addressed byte indicated. No flags are affected. Example: The Stack Pointer originally contains the value 32H, and internal RAM locations 30H through 32H contain the values 20H, 23H, and 01H, respectively.
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The 8051 Instruction Set 1.14.39 RET Function: Return from subroutine Description: RET pops the high- and low-order bytes of the PC successively from the stack, decrementing the Stack Pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL. No flags are affected. Example: The Stack Pointer originally contains the value 0BH. Internal RAM locations 0AH and 0BH contain the values 23H and 01H, respectively.
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The 8051 Instruction Set 1.14.41 RL A Function: Rotate Accumulator Left Description: The eight bits in the Accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected. Example: The Accumulator holds the value 0C5H (11000101B). The following instruction, RL A leaves the Accumulator holding the value 8BH (10001011B) with the carry unaffected. Bytes: 1 Cycles: 1 Encoding: 0 0 1 0 0 0 1 1 Operation: RL (An + 1) ← (An) n = 0 - 6 (A0) ← (A7) 1.14.
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The 8051 Instruction Set 1.14.43 RR A Function: Rotate Accumulator Right Description: The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected. Example: The Accumulator holds the value 0C5H (11000101B). The following instruction, RR A leaves the Accumulator holding the value 0E2H (11100010B) with the carry unaffected. Bytes: 1 Cycles: 1 Encoding: 0 0 0 0 0 0 1 1 Operation: RR (An) ← (An + 1) n = 0 - 6 (A7) ← (A0) 1.14.
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The 8051 Instruction Set 1.14.45 SETB Function: Set Bit Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit. No other flags are affected. Example: The carry flag is cleared. Output Port 1 has been written with the value 34H (00110100B). The following instructions, SETB C SETB P1.0 sets the carry flag to 1 and changes the data output on Port 1 to 35H (00110101B).
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The 8051 Instruction Set 1.14.47 SUBB A, Function: Subtract with borrow Description: SUBB subtracts the indicated variable and the carry flag together from the Accumulator, leaving the result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7 and clears C otherwise.
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The 8051 Instruction Set SUBB A,#data Bytes: 2 Cycles: 1 Encoding: 1 0 0 1 0 1 0 0 immediate data Operation: SUBB (A) ← (A) - (C) - #data 1.14.48 SWAP A Function: Swap nibbles within the Accumulator Description: SWAP A interchanges the low- and high-order nibbles (four-bit fields) of the Accumulator (bits 3 through 0 and bits 7 through 4). The operation can also be thought of as a 4-bit rotate instruction. No flags are affected. Example: The Accumulator holds the value 0C5H (11000101B).
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The 8051 Instruction Set Bytes: 2 Cycles: 1 Encoding: 1 1 0 0 0 1 0 1 0 0 0 1 1 i direct address Operation: XCH (A) D (direct) XCH A,@Ri Bytes: 1 Cycles: 1 Encoding: 1 1 Operation: XCH (A) D ((Ri)) 1.14.50 XCHD A,@Ri Function: Exchange Digit Description: XCHD exchanges the low-order nibble of the Accumulator (bits 3 through 0), generally representing a hexadecimal or BCD digit, with that of the internal RAM location indirectly addressed by the specified register.
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The 8051 Instruction Set 1.14.51 XRL , Function: Logical Exclusive-OR for byte variables Description: XRL performs the bitwise logical Exclusive-OR operation between the indicated variables, storing the results in the destination. No flags are affected. The two operands allow six addressing mode combinations.
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The 8051 Instruction Set XRL A,@#data Bytes: 2 Cycles: 1 Encoding: 0 1 1 0 0 1 0 0 immediate data 0 0 0 1 0 direct address 0 0 1 1 direct address Operation: XRL (A) ← (A) V #data XRL direct,A Bytes: 2 Cycles: 1 Encoding: 0 1 1 Operation: XRL (direct) ← (direct) V (A) XRL direct,#data Bytes: 3 Cycles: 2 Encoding: 0 1 1 0 immediate data Operation: XRL (direct) ← (direct) V #data 1-63 4316E–8051–01/07 Atmel 8051 Microcontrollers Hardware Manual
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Section 2 Common Features Description 2.1 Introduction This chapter presents a comprehensive description of the on-chip hardware features of the Atmel 8051 microcontrollers. Included in this description are: The port drivers and how they function both as ports and, for Ports 0 and 2, in bus operations The Timer/Counters The serial Interface The Interrupt System Reset The reduced Power Modes Atmel 8051 Microcontrollers Hardware Manual 2-66 Rev.
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Common Features Description Figure 2-1. 8051 Architecture Block Diagram Note: (*)For Timer 2 only. Figure 2-1 shows a functional block diagram of the 80C51s.
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Common Features Description 2.2 Special Function Registers A map of the on-chip memory area called SFR (Special Function Register) space is shown in Figure 2-1. SFRs marked by parentheses are resident in the microcontroller which have the Timer2 feature.Note that not all of the addresses are occupied. Read accesses to these addresses will in general return random data.
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Common Features Description 2.2.3 Program Status Word The PSW register contains program status information as detailed in Table 2-1. Table 2-1. PSW: Program Status Word Register (MSB) (LSB) CY AC F0 RS1 RS0 OV - Symbol Position CY PSW.7 Carry flag AC PSW.6 Auxiliary Carry flag. (For BCD operations.) F0 PSW.5 Flag 0 (Available to the user for general purposes.) P Name and Significance Register bank Select control bits 1 & 0.
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Common Features Description RCAP2H and RCAP2L hold the reload value for this mode. More about Timer 2’s features in Section 1.6. 2.2.10 Control Registers Special Function Registers IP, IE, TMOD, TCON, T2CON, SCON, and PCON contain control and status bits for the interrupt system, the timer/counters, and the serial port. They are described in later sections. 2.
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Common Features Description 2.4 CPU Timing 2.4.1 X1 Mode (Standard Mode) A machine cycle consists of 6 states (12 oscillator periods). Each state is divided into a Phase 1 half, during which the Phase 1 clock is active, and a Phase 2 half, during which the Phase 2 clock is active. Thus, a machine cycle consists of 12 oscillator periods, numbered S1P1 (State 1, Phase 1), through S6P2 (State 6, Phase 2). Each phase lasts for one oscillator period. Each state lasts for two oscillator periods.
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Common Features Description Figure 2-3. 80C51 Fetch/Execute Sequences. 2.4.2 X2 Mode This section not yet available.
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Common Features Description 2.5 Port Structures and Operation All four ports in the 80C51 are bidirectional. Each consists of a latch (Special Function Register P0 through P3), an output driver, and an input buffer. The output drivers of Ports 0 and 2, and input buffers of Port 0, are used in accesses to external memory. In this application, Port 0 outputs the low byte of the external memory address, time-multiplexed with the byte being written or read.
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Common Features Description Figure 2-4. 80C51 Port Bit Latches and I/O Buffers. As shown in Figure 2-4, the output drivers of Ports 0 and 2 are switchable to an internal ADDR and ADDR/DATA bus by an internal CONTROL signal for use in external memory accesses. During external memory accesses, the P2 SFR remains unchanged, but the P0 SFR gets 1s written to it.
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Common Features Description in the data sheets) when externally pulled low. Port 0, on the other hand, is considered “true” bidirectional, because when configured as an input it floats. All the port latches in the 80C51 have 1’s written to them by the reset function. If a 0 is subsequently written to a port latch, it can be re configured as an input by writing a 1 to it. 2.5.
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Common Features Description 2.5.3 Port Loading and Interfacing The output buffer of Ports 1, 2 and 3 can each drive 3LS TTL inputs. The pins can be driven by open-collector and open-drain outputs, but note that 0-to-1 transition will not be fast. In the CMOS device, an input 0 turns off pull-up P3, leaving only the weak pullup P2 to drive the transistor. Figure 2-6 shows an example where the port is driven by an open drain transistor tN. The parasitic capacitance is equal to 1000pF. Figure 2-6.
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Common Features Description DJNZ (decrement and jump if not zero, e.g., DJNZ P3, LABEL) MOV PX.Y,C(move carry bit to bit Y of Port X) CLR PX.Y(clear bit Y of Port X) SETB PX.Y(set bit Y of Port X) It is not obvious that the last three instructions in this list are read-modify-write instructions, but they are. They read the port byte, all 8 bits, modify the addressed bit, then write the new byte back to the latch.
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Common Features Description When the CPU is executing out of external Program Memory, all 8 bits of Port 2 are dedicated to an output function and may not be used for general purpose I/O. During external program fetches they output the high byte of the PC. During this time the Port 2 drivers use the strong pull-ups to emit PC bits that are 1’s. Figure 2-8. External Program Memory Execution 2.7 PSEN The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches.
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Common Features Description 2.8 ALE The main function of ALE is to provide a properly timed signal to latch the low byte of an address from P0 to an external latch during fetches from external Program Memory. For that purpose ALE is activated twice every machine cycle. This activation takes place even when the cycle involves no external fetch. The only time an ALE pulse doesn’t come out is during an access to external Data Memory. The first ALE of the second cycle of a MOVX instructions is missing.
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Common Features Description Table 2-2. AUXR Register Auxillary Register - AUXR (S:8Eh) 7 6 5 4 3 2 1 0 - - - - - - EXTRAM AO Bit Bit Number Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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Common Features Description 2.9 Timer/Counters The Atmel 80C51 Microcontrollers implement two general purpose, 16-bit timers/counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a timer or as an event counter. When operating as a timer, the timer/counter runs for a programmed length of time, then issues an interrupt request. When operating as a counter, the timer/counter counts negative transitions on an external pin.
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Common Features Description 2.10 Timer 0 Timer 0 functions as either a timer or event counter in four modes of operation. Figure 29 to Figure 2-12 show the logical configuration of each mode. Timer 0 is controlled by the four lower bits of the TMOD register (see Table 2-5) and bits 0, 1, 4 and 5 of the TCON register (see Table 2-3). TMOD register selects the method of timer gating (GATE0), timer or counter operation (T/C0#) and mode of operation (M10 and M00).
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Common Features Description Figure 2-10. Timer/Counter x (x = 0 or 1) in Mode 1 PERIPH CLOCK ÷6 0 THx (8 bits) 1 TLx (8 bits) Overflow TFx TCON reg Timer x Interrupt Request Tx C/Tx# TMOD reg INTx# TRx TCON reg GATE 2.10.3 Mode 2 (8-bit Timer with Auto-Reload) Mode 2 configures timer 0 as an 8-bit timer (TL0 register) that automatically reloads from the TH0 register (see Table 2-5 on page 87).
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Common Features Description Figure 2-12. Timer/Counter 0 in Mode 3: Two 8-bit Counters PERIPH CLOCK ÷6 0 1 TL0 (8 bits) Overflow TH0 (8 bits) Overflow TF0 TCON.5 Timer 0 Interrupt Request TF1 TCON.7 Timer 1 Interrupt Request T0 C/T0# TMOD.2 INT0# TR0 TCON.4 GATE PERIPH CLOCK ÷6 TR1 TCON.6 2.11 2.11.1 Timer 1 Mode 0 (13-bit Timer) Timer 1 is identical to timer 0, except for mode 3, which is a hold-count mode.
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Common Features Description Figure 2-13. Timer/Counter 1 Mode 0: 13-bit Counter Periph Clock /6 2.11.2 Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit timer with the TH1 and TL1 registers connected in cascade (see Figure 2-10). The selected input increments the TL1 register. 2.11.3 Mode 2 (8-bit Timer with Auto Reload) Mode 2 configures Timer 1 as an 8-bit timer (TL1 register) with automatic reload from the TH1 register on overflow (see Figure 2-11).
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Common Features Description Figure 2-15. Timer Interrupt System Timer 0 Interrupt Request TF0 TCON.5 ET0 IE0.1 Timer 1 Interrupt Request TF1 TCON.7 ET1 IE0.3 2.11.6 Timer Registers Table 2-3. TCON Register - TCON (S:88h) Timer/Counter Control Register. 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic Description 7 TF1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine.
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Common Features Description Table 2-4. TMOD Register - TMOD (S: 89h) TMOD - Timer/Counter 0 and 1 Modes 7 6 5 4 3 2 1 0 GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Number Bit Mnemonic Description 7 GATE1 Timer 1 Gating Control Bit Clear to enable timer 1 whenever the TR1 bit is set. Set to enable timer 1 only while the INT1# pin is high and TR1 bit is set. 6 C/T1# Timer 1 Counter/Timer Select Bit Clear for timer operation: timer 1 counts the divided-down system clock.
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Common Features Description Table 2-6. TL0 Register - TL0 (S:8Ah) Timer 0 Low Byte Register 7 Bit Number 6 5 4 3 2 1 0 3 2 1 0 3 2 1 0 Bit Mnemonic Description Low Byte of Timer 0. 7:0 Reset Value = 0000 0000b Table 2-7. TH1 Register - TH1 (S:8Dh) Timer 1 High Byte Register 7 Bit Number 6 5 4 Bit Mnemonic Description High Byte of Timer 1. 7:0 Reset Value = 0000 0000b Table 2-8.
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Common Features Description 2.12 Timer 2 Timer 2 is a 16-bit timer/counter which is present in most of the Atmel 8051 microcontrollers.The count is maintained by two 8-bit timer registers, TH2 and TL2, that are cascade connected. Like Timers 0 and 1, it can operate either as a timer or as an event counter. It is controlled by the T2CON register (See Table 2-9) and the T2MOD register (See Table 2-10). Timer 2 operation is similar to Timer 0 and Timer 1.
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Common Features Description but with the added feature that a 1-to-0 transition at external input T2EX will also trigger the 16-bit reload and set EXF2. 2.12.1 Auto-reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. This feature is controlled by the DCEN bit in the T2MOD register (See Table 2-10). Setting the DCEN bit enables timer 2 to count up or down as shown in Figure 2-17. In this mode the T2EX pin controls the counting direction.
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Common Features Description depending on the system oscillator frequency and the value in the RCAP2H and RCAP2L registers: F × 2 x2 osc Clock – OutFrequency = ----------------------------------------------------------------------------------------2 × ( 65536 – RCAP2H ⁄ RCAP2L ) Note: X2 bit is located in the CKCON register. In X2 mode, FOSC=FXTAL. In standard mode, FOSC=FXTAL/2. For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz (FOSC/216) to 4 MHz (FOSC/4).
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Common Features Description 2.12.3 Timer Registers Table 2-9. T2CON Register - T2CON (S:C8h) Timer 2 Control Register 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number 7 Bit Mnemonic Description TF2 Timer 2 overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on timer 2 overflow. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
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Common Features Description Table 2-10. T2MOD Register - T2MOD (S:C9h) Timer 2 Mode Control Register 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate.
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Common Features Description Table 2-12. TL2 Register - TL2 (S:CCh) Timer 2 Low Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7:0 Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Table 2-13. RCAP2H Register -RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic Description 7:0 High Byte of Timer 2 Reload/Capture.
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Common Features Description The serial port can operate in 4 modes: Mode 0: Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted/received: 8 data bits (LSB first). The baud rate is fixed at 1/12 the oscillator frequency. Mode 1: 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable.
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Common Features Description 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) FE Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit 7 SM0 Serial port Mode bit 0 Refer to SM1 for serial port mode selection.
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Common Features Description 2.13.1 Baud Rates The baud rate in Mode 0 is fixed: The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON. If SMOD = 0 (which is its value on reset), the baud rate is 1/64 the oscillator frequency. If SMOD = 1, the baud rate is 1/32 the oscillator frequency. In the 80C51, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate.
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Common Features Description 2.13.3 Internal Baud Rate Generator (BRG) When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register. Figure 2-20.
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Common Features Description The baud rate generator can be used for mode 1 or 3 (refer to Figure 2-22 on page 100), but also for mode 0 for UART, thanks to the bit SRC located in BDRCON register (Table 2-29.) 2.13.4 Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: The Timer 1 interrupt should be disabled in this application.
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Common Features Description 2.13.5 Using Timer 2 to Generate Baud Rates Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2-9). Note then the baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 2-22. Figure 2-22. Timer 2 in Baud Rate Generator Mode.
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Common Features Description Figure 2-23. Timer 2 Generated Commonly Used Baud Rates Fosc (MHz) 6 11.0592 12 16 Baudrate (RCAP2H RACP2L) 110 F9-57 EE-3F 300 FD-8F FB-80 FB-1E F9-7D 600 FE-C8 FD-C0 FD-8F FC-BF 1200 FF-64 FE-E0 FE-C8 FE-5F 2400 FF-B2 FF-70 FF-64 FF-30 4800 FF-D9 FF-B8 FF-B2 FF-98 9600 FF-DC FF-D9 FF-CC 19200 FF-EE FF-E6 38400 FF-F7 FF-F3 56800 FF-FA XX-XX are values of RCAP2H-RCAP2L 2.13.
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Common Features Description As data bits come in from the right, 1’s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift and load SBUF. At S1P1 of the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared and RI is set. 2.13.7 More About Mode 1 Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1).
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Common Features Description Figure 2-24.
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Common Features Description 2.14 Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (see Figure 2-25). Figure 2-25.
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Common Features Description 2.15 Automatic Address Recognition 2.15.1 Multiprocessor Communications Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices.
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Common Features Description Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit.
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Common Features Description Table 2-17. SADEN Register SADEN - Slave Address Mask Register (B9h) 7 6 5 4 3 2 1 0 3 2 1 0 Reset Value = 0000 0000b Not bit addressable Table 2-18.
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Common Features Description UART Registers Table 2-19. SCON Register SCON - Serial Control Register (98h) 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1) FE Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit 7 SM0 Serial port Mode bit 0 Refer to SM1 for serial port mode selection.
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Common Features Description Table 2-20. SADEN Register SADEN - Slave Address Mask Register for UART (B9h) 7 6 5 4 3 2 1 0 3 2 1 0 3 2 1 0 Reset Value = 0000 0000b Table 2-21. SADDR Register SADDR - Slave Address Register for UART (A9h) 7 6 5 4 Reset Value = 0000 0000b Table 2-22. SBUF Register SBUF - Serial Buffer Register for UART (99h) 7 6 5 4 Reset Value = XXXX XXXXb Table 2-23.
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Common Features Description Table 2-24. T2CON Register T2CON - Timer2 Control Register (C8h) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Bit Number Mnemonic 7 TF2 Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
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Common Features Description Table 2-25. PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Bit Number Mnemonic 7 SMOD1 6 SMOD0 5 - 4 POF Power-Off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage.
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Common Features Description Table 2-26. BDRCON Register BDRCON - Baud Rate Control Register (9Bh) 7 6 5 4 3 2 1 0 - - - BRR TBCK RBCK SPD SRC Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit 6 - Reserved The value read from this bit is indeterminate. Do not set this bit 5 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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Common Features Description Note that the "priority within level" structure is only used to resolve simultaneous requests of the same priority level. 2.16.1 How Interrupts Are Handled The interrupt flags are sampled at SsP2 of every machine cycle. The samples are polled during the following machine cycle.
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Common Features Description The hardware-generated LCALL pushes the contents of the Program Counter onto the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to, as shown below. Source Vector Address IE0 0003H TF0 000BH IE1 0013H TF1 001BH RI + TI 0023H TF2 + EXF2 002BH Execution proceeds from that location until the RETI instruction is encountered.
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Common Features Description complete the instruction in progress, plus 4 cycles to complete the next instruction if the instruction is MUL or DIV). Thus, in a single-interrupt system, the response time is always more than 3 cycles and less than 8 cycles.
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