Datasheet
Table Of Contents
- Features
- 1. Ordering Information
- 2. Typical Applications
- 3. Pinout and Block Diagram
- 4. Overview
- 5. Resources
- 6. Capacitive Touch Sensing
- 7. CPU
- 8. Memories
- 9. EDMA – Enhanced DMA Controller
- 10. Event System
- 11. System Clock and Clock options
- 11.1 Features
- 11.2 Overview
- 11.3 Clock Sources
- 11.3.1 32kHz Ultra Low Power Internal Oscillator
- 11.3.2 32.768kHz Calibrated Internal Oscillator
- 11.3.3 32.768kHz Crystal Oscillator
- 11.3.4 0.4 - 16MHz Crystal Oscillator
- 11.3.5 8MHz Calibrated Internal Oscillator
- 11.3.6 32MHz Run-time Calibrated Internal Oscillator
- 11.3.7 External Clock Sources
- 11.3.8 PLL with 1x-31x Multiplication Factor
- 12. Power Management and Sleep Modes
- 13. System Control and Reset
- 14. WDT – Watchdog Timer
- 15. Interrupts and Programmable Multilevel Interrupt Controller
- 16. I/O Ports
- 17. Timer Counter Type 4 and 5
- 18. WeX – Waveform Extension
- 19. Hi-Res – High Resolution Extension
- 20. Fault Extension
- 21. RTC – 16-bit Real-Time Counter
- 22. TWI – Two-Wire Interface
- 23. SPI – Serial Peripheral Interface
- 24. USART
- 25. IRCOM – IR Communication Module
- 26. XCL – XMEGA Custom Logic Module
- 27. CRC – Cyclic Redundancy Check Generator
- 28. ADC – 12-bit Analog to Digital Converter
- 29. DAC – Digital to Analog Converter
- 30. AC – Analog Comparator
- 31. Programming and Debugging
- 32. Pinout and Pin Functions
- 33. Peripheral Module Address Map
- 34. Instruction Set Summary
- 35. Packaging Information
- 36. Electrical Characteristics
- 36.1 Absolute Maximum Ratings
- 36.2 General Operating Ratings
- 36.3 Current Consumption
- 36.4 Wake-up Time from Sleep Modes
- 36.5 I/O Pin Characteristics
- 36.6 ADC Characteristics
- 36.7 DAC Characteristics
- 36.8 Analog Comparator Characteristics
- 36.9 Bandgap and Internal 1.0V Reference Characteristics
- 36.10 External Reset Characteristics
- 36.11 Power-on Reset Characteristics
- 36.12 Flash and EEPROM Characteristics
- 36.13 Clock and Oscillator Characteristics
- 36.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics
- 36.13.2 Calibrated 8MHz Internal Oscillator Characteristics
- 36.13.3 Calibrated and Tunable 32MHz Internal Oscillator Characteristics
- 36.13.4 32 kHz Internal ULP Oscillator Characteristics
- 36.13.5 Internal Phase Locked Loop (PLL) Characteristics
- 36.13.6 External Clock Characteristics
- 36.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics
- 36.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics
- 36.14 SPI Characteristics
- 36.15 Two-Wire Interface Characteristics
- 37. Typical Characteristics
- 37.1 Current Consumption
- 37.2 I/O Pin Characteristics
- 37.3 ADC Characteristics
- 37.4 DAC Characteristics
- 37.5 AC Characteristics
- 37.6 Internal 1.0V Reference Characteristics
- 37.7 BOD Characteristics
- 37.8 External Reset Characteristics
- 37.9 Power-on Reset Characteristics
- 37.10 Oscillator Characteristics
- 37.11 Two-wire Interface Characteristics
- 37.12 PDI Characteristics
- 38. Errata – ATxmega32E5 / ATxmega16E5 / ATxmega8E5
- 39. Revision History
- Table of Contents
66
XMEGA E5 [DATASHEET]
Atmel-8153J–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–11/2014
SPM Z+ Store Program Memory and Post-Increment by 2
(RAMPZ:Z)
Z
R1:R0,
Z + 2
None -
IN Rd, A In From I/O Location Rd
I/O(A) None 1
OUT A, Rr Out To I/O Location I/O(A)
Rr None 1
PUSH Rr Push Register on Stack STACK
Rr None 1
(1)
POP Rd Pop Register from Stack Rd
STACK None 2
(1)
XCH Z, Rd Exchange RAM location
Tem p
Rd
(Z)
Rd,
(Z),
Tem p
None 2
LAS Z, Rd Load and Set RAM location
Tem p
Rd
(Z)
Rd,
(Z),
Temp v (Z)
None 2
LAC Z, Rd Load and Clear RAM location
Tem p
Rd
(Z)
Rd,
(Z),
($FFh – Rd)
(Z)
None 2
LAT Z, Rd Load and Toggle RAM location
Tem p
Rd
(Z)
Rd,
(Z),
Tem p (Z)
None 2
Bit and bit-test instructions
LSL Rd Logical Shift Left
Rd(n+1)
Rd(0)
C
Rd(n),
0,
Rd(7)
Z,C,N,V,H 1
LSR Rd Logical Shift Right
Rd(n)
Rd(7)
C
Rd(n+1),
0,
Rd(0)
Z,C,N,V 1
ROL Rd Rotate Left Through Carry
Rd(0)
Rd(n+1)
C
C,
Rd(n),
Rd(7)
Z,C,N,V,H 1
ROR Rd Rotate Right Through Carry
Rd(7)
Rd(n)
C
C,
Rd(n+1),
Rd(0)
Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n)
Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)
Rd(7..4) None 1
BSET s Flag Set SREG(s)
1 SREG(s) 1
BCLR s Flag Clear SREG(s)
0 SREG(s) 1
SBI A, b Set Bit in I/O Register I/O(A, b)
1 None 1
CBI A, b Clear Bit in I/O Register I/O(A, b)
0 None 1
BST Rr, b Bit Store from Register to T T
Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b)
T None 1
SEC Set Carry C
1 C 1
CLC Clear Carry C
0 C 1
SEN Set Negative Flag N
1 N 1
CLN Clear Negative Flag N
0 N 1
SEZ Set Zero Flag Z
1 Z 1
CLZ Clear Zero Flag Z
0 Z 1
SEI Global Interrupt Enable I
1 I 1
Mnemonics Operands Description Operation Flags #Clocks