Datasheet

ManualsBrandsAtmel ManualsComputer HardwareAVR XMEGA 8/16-bit High Performance Low Power Flash Microcontrollers

Table Of Contents

Features
1. Ordering Information
2. Typical Applications
3. Pinout and Block Diagram
4. Overview
5. Resources
- 5.1 Recommended Reading
6. Capacitive Touch Sensing
7. CPU
- 7.1 Features
- 7.2 Overview
- 7.3 Architectural Overview
- 7.4 ALU - Arithmetic Logic Unit
  - 7.4.1 Hardware Multiplier
- 7.5 Program Flow
- 7.6 Status Register
- 7.7 Stack and Stack Pointer
- 7.8 Register File
8. Memories
- 8.1 Features
- 8.2 Overview
- 8.3 Flash Program Memory
- 8.4 Fuses and Lock Bits
- 8.5 Data Memory
- 8.6 EEPROM
- 8.7 I/O Memory
  - 8.7.1 General Purpose I/O Registers
- 8.8 Data Memory and Bus Arbitration
- 8.9 Memory Timing
- 8.10 Device ID and Revision
- 8.11 I/O Memory Protection
- 8.12 Flash and EEPROM Page Size
9. EDMA – Enhanced DMA Controller
- 9.1 Features
- 9.2 Overview
10. Event System
- 10.1 Features
- 10.2 Overview
11. System Clock and Clock options
- 11.1 Features
- 11.2 Overview
- 11.3 Clock Sources
12. Power Management and Sleep Modes
- 12.1 Features
- 12.2 Overview
- 12.3 Sleep Modes
13. System Control and Reset
- 13.1 Features
- 13.2 Overview
- 13.3 Reset Sequence
- 13.4 Reset Sources
14. WDT – Watchdog Timer
- 14.1 Features
- 14.2 Overview
15. Interrupts and Programmable Multilevel Interrupt Controller
- 15.1 Features
- 15.2 Overview
- 15.3 Interrupt Vectors
16. I/O Ports
- 16.1 Features
- 16.2 Overview
- 16.3 Output Driver
- 16.4 Input Sensing
- 16.5 Alternate Port Functions
17. Timer Counter Type 4 and 5
- 17.1 Features
- 17.2 Overview
18. WeX – Waveform Extension
- 18.1 Features
- 18.2 Overview
19. Hi-Res – High Resolution Extension
- 19.1 Features
- 19.2 Overview
20. Fault Extension
- 20.1 Features
- 20.2 Overview
21. RTC – 16-bit Real-Time Counter
- 21.1 Features
- 21.2 Overview
22. TWI – Two-Wire Interface
- 22.1 Features
- 22.2 Overview
23. SPI – Serial Peripheral Interface
- 23.1 Features
- 23.2 Overview
24. USART
- 24.1 Features
- 24.2 Overview
25. IRCOM – IR Communication Module
- 25.1 Features
- 25.2 Overview
26. XCL – XMEGA Custom Logic Module
- 26.1 Features
- 26.2 Overview
27. CRC – Cyclic Redundancy Check Generator
- 27.1 Features
- 27.2 Overview
28. ADC – 12-bit Analog to Digital Converter
- 28.1 Features
- 28.2 Overview
29. DAC – Digital to Analog Converter
- 29.1 Features
- 29.2 Overview
30. AC – Analog Comparator
- 30.1 Features
- 30.2 Overview
31. Programming and Debugging
- 31.1 Features
- 31.2 Overview
32. Pinout and Pin Functions
- 32.1 Alternate Pin Function Description
- 32.2 Alternate Pin Functions
33. Peripheral Module Address Map
34. Instruction Set Summary
35. Packaging Information
- 35.1 32A
- 35.2 32Z
- 35.3 32MA
36. Electrical Characteristics
- 36.1 Absolute Maximum Ratings
- 36.2 General Operating Ratings
- 36.3 Current Consumption
- 36.4 Wake-up Time from Sleep Modes
- 36.5 I/O Pin Characteristics
- 36.6 ADC Characteristics
- 36.7 DAC Characteristics
- 36.8 Analog Comparator Characteristics
- 36.9 Bandgap and Internal 1.0V Reference Characteristics
  - 36.9.1 Brownout Detection Characteristics
- 36.10 External Reset Characteristics
- 36.11 Power-on Reset Characteristics
- 36.12 Flash and EEPROM Characteristics
- 36.13 Clock and Oscillator Characteristics
- 36.14 SPI Characteristics
- 36.15 Two-Wire Interface Characteristics
37. Typical Characteristics
- 37.1 Current Consumption
- 37.2 I/O Pin Characteristics
- 37.3 ADC Characteristics
- 37.4 DAC Characteristics
- 37.5 AC Characteristics
- 37.6 Internal 1.0V Reference Characteristics
- 37.7 BOD Characteristics
- 37.8 External Reset Characteristics
- 37.9 Power-on Reset Characteristics
- 37.10 Oscillator Characteristics
- 37.11 Two-wire Interface Characteristics
- 37.12 PDI Characteristics
38. Errata – ATxmega32E5 / ATxmega16E5 / ATxmega8E5
- 38.1 Rev. B
- 38.2 Rev. A
39. Revision History
- 39.1 8153J – 11/2014
- 39.2 8153I – 08/2014
- 39.3 8153H – 07/2014
- 39.4 8153G – 10/2013
- 39.5 8153F – 08/2013
- 39.6 8153E – 06/2013
- 39.7 8153D – 06/2013
- 39.8 8153C – 05/2013
- 39.9 8153B – 04/2013
- 39.10 8153A – 04/2013
Table of Contents

XMEGA E5 [DATASHEET]

Atmel-8153J–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–11/2014

18. WeX – Waveform Extension

18.1 Features

 Module for more customized and advanced waveform generation

 Optimized for various type of motor, ballast, and power stage control

 Output matrix for timer/counter waveform output distribution

 Configurable distribution of compare channel output across port pins

 Redistribution of dead-time insertion resource between TC4 and TC5

 Four dead-time insertion (DTI) units, each with

 Complementary high and low side with non overlapping outputs

 Separate dead-time setting for high and low side

 8-bit resolution

 Four swap (SWAP) units

 Separate port pair or low high side drivers swap

 Double buffered swap feature

 Pattern generation creating synchronized bit pattern across the port pins

 Double buffered pattern generation

18.2 Overview

The waveform extension (WEX) provides extra functions to the timer/counter in waveform generation (WG) modes. It is

primarily intended for motor control, ballast, LED, H-bridge, power converters, and other types of power control

applications. The WEX consist of five independent and successive units, as shown in Figure 18-1.

Figure 18-1. Waveform Extension and Closely Related Peripherals

The output matrix (OTMX) can distribute and route out the waveform outputs from timer/counter 4 and 5 across the port

pins in different configurations, each optimized for different application types. The dead time insertion (DTI) unit splits the

four lower OTMX outputs into a two non-overlapping signals, the non-inverted low side (LS) and inverted high side (HS)

of the waveform output with optional dead-time insertion between LS and HS switching.

The swap (SWAP) unit can swap the LS and HS pin position. This can be used for fast decay motor control. The pattern

generation unit generates synchronized output waveform with constant logic level. This can be used for easy stepper

motor and full bridge control.

SWAP1DTI1

Pattern Generator

Output Matrix

WEX

Px7

Px6

Px5

Px4

Px3

Px2

Px1

Px0

Fault

Unit 5

Fault

Unit 4

T/C4

T/C5

OUTOVDIS

HIRES