Datasheet

25
XMEGA E5 [DATASHEET]
Atmel-8153J–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–11/2014
13. System Control and Reset
13.1 Features
 Reset the microcontroller and set it to initial state when a reset source goes active
 Multiple reset sources that cover different situations
 Power-on reset
 External reset
 Watchdog reset
 Brownout reset
 PDI reset
 Software reset
 Asynchronous operation
 No running system clock in the device is required for reset
 Reset status register for reading the reset source from the application code
13.2 Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset
source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins
are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their
initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of
the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
13.3 Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
 Reset counter delay
 Oscillator startup
 Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
13.4 Reset Sources
13.4.1 Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (V
POT
), and this will start the reset sequence.
The POR is also activated to power down the device properly when the V
CC falls and drops below the VPOT level. The
V
POT level is higher for falling V
CC
than for rising V
CC
. Consult the datasheet for POR characteristics data.