Datasheet

14
XMEGA E5 [DATASHEET]
Atmel-8153J–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–11/2014
8.5 Data Memory
The data memory contains the I/O memory, internal SRAM and EEPROM. The data memory is organized as one
continuous memory section, see Table 8-2 on page 15. To simplify development, I/O Memory, EEPROM and SRAM will
always have the same start addresses for all XMEGA devices.
Figure 8-2. Data Memory Map (hexadecimal value)
8.6 EEPROM
Atmel AVR XMEGA E5 devices have EEPROM for nonvolatile data storage. It is memory mapped and accessed in
normal data space. The EEPROM supports both byte and page access. EEPROM allows highly efficient EEPROM
reading and EEPROM buffer loading. When doing this, EEPROM is accessible using load and store instructions.
EEPROM will always start at hexadecimal address 0x1000.
8.7 I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules in XMEGA E5 is shown in the “Peripheral Module Address Map”
on page 61.
8.7.1 General Purpose I/O Registers
The lowest four I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
8.8 Data Memory and Bus Arbitration
Since the data memory is organized as three separate sets of memories, the different bus masters (CPU, EDMA
controller read and EDMA controller write, etc.) can access different memory sections at the same time.
8.9 Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. For burst read (EDMA), new data are available every cycle. EEPROM page load (write) takes
one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the
instruction summary for more details on instructions and instruction timing.
Byte Address ATxmega32E5 Byte Address ATxmega16E5 Byte Address ATxmega8E5
0
I/O Registers (4K)
0
I/O Registers (4K)
0
I/O Registers (4K)
FFF FFF FFF
1000
EEPROM (1K)
1000
EEPROM (512B)
1000
EEPROM (512B)
13FF 11FF 11FF
RESERVED RESERVED RESERVED
2000
Internal SRAM (4K)
2000
Internal SRAM (2K)
2000
Internal SRAM (2K)
2FFF 27FF 27FF