Specifications

68
AT90S8515
0841G–09/01
Figure 47. Port B Schematic Diagram (Pins PB2 and PB3)
Figure 48. Port B Schematic Diagram (Pin PB4)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB4
SPI SS
MSTR
SPE
WP:
WD:
RL:
RP:
RD:
MSTR:
SPE:
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI MASTER ENABLE
SPI ENABLE
DDB4
PORTB4
RL
RP