Specifications

62
AT90S8515
0841G–09/01
Figure 44. External Data SRAM Memory Cycles with Wait State
System Clock Ø
ALE
WR
RD
Data/Address [7..0]
Data/Address [7..0]
Address [15..8]
Address
Address
Address
T1 T2 T3 T4
Prev. Address
Prev. Address
Prev. Address
Data
Data
Writ
e
R
e
a
d
Addr.
Addr.