Specifications

AT90S8515

0841G–09/01

Timer/Counter Interrupt Flag

• Bit 7 – TOV1: Timer/Counter1 Overflow Flag

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by

hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG, TOIE1

(Timer/Counter1 Overflow Interrupt Enable) and TOV1 are set (one), the

Timer/Counter1 Overflow interrupt is executed. In PWM mode, this bit is set when

Timer/Counter1 changes counting direction at $0000.

• Bit 6 – OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1

and the data in OCR1A (Output Compare Register 1A). OCF1A is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, OCF1A is

cleared by writing a logical “1” to the flag. When the I-bit in SREG, OCIE1A

(Timer/Counter1 Compare Match InterruptA Enable) and the OCF1A are set (one), the

Timer/Counter1 CompareA Match interrupt is executed.

• Bit 5 – OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1

and the data in OCR1B (Output Compare Register 1B). OCF1B is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, OCF1B is

cleared by writing a logical “1” to the flag. When the I-bit in SREG, OCIE1B

(Timer/Counter1 Compare Match InterruptB Enable) and the OCF1B are set (one), the

Timer/Counter1 CompareB Match interrupt is executed.

• Bit 4 – Res: Reserved Bit

This bit is a reserved bit in the AT90S8515 and always reads zero.

• Bit 3 – ICF1: Input Capture Flag 1

The ICF1 bit is set (one) to flag an input capture event, indicating that the

Timer/Counter1 value has been transferred to the input capture register (ICR1). ICF1 is

cleared by hardware when executing the corresponding interrupt handling vector. Alter-

natively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TICIE1

(Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the

Timer/Counter1 Capture interrupt is executed.

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the AT90S8515 and always reads zero.

• Bit 1 – TOV: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0

(Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set (one), the

Timer/Counter0 Overflow interrupt is executed.

• Bit 0 – Res: Reserved Bit

This bit is a reserved bit in the AT90S8515 and always reads zero.

Bit 7 6 5 4 3 2 1 0

$38 ($58) TOV1 OCF1A OCIFB – ICF1 – TOV0 – TIFR

Read/Write R/W R/W R/W R R/W R R/W R

Initial Value 0 0 0 0 0 0 0 0