Datasheet

viii
8331B–AVR–03/12
Atmel AVR XMEGA AU
21.13 Register Summary - TWI Slave .....................................................................286
21.14 Interrupt Vector Summary .............................................................................286
22 SPI – Serial Peripheral Interface ......................................................... 287
22.1 Features ........................................................................................................287
22.2 Overview ........................................................................................................287
22.3 Master Mode ..................................................................................................288
22.4 Slave Mode ....................................................................................................288
22.5 Data Modes ...................................................................................................289
22.6 DMA Support .................................................................................................289
22.7 Register Description ......................................................................................290
22.8 Register Summary .........................................................................................292
22.9 Interrupt vector Summary ..............................................................................292
23 USART ................................................................................................... 293
23.1 Features ........................................................................................................293
23.2 Overview ........................................................................................................293
23.3 Clock Generation ...........................................................................................295
23.4 Frame Formats ..............................................................................................298
23.5 USART Initialization .......................................................................................299
23.6 Data Transmission - The USART Transmitter ...............................................299
23.7 Data Reception - The USART Receiver ........................................................300
23.8 Asynchronous Data Reception ......................................................................301
23.9 Fractional Baud Rate Generation ..................................................................304
23.10 USART in Master SPI Mode ..........................................................................307
23.11 USART SPI vs. SPI .......................................................................................307
23.12 Multiprocessor Communication Mode ...........................................................307
23.13 IRCOM Mode of Operation ............................................................................308
23.14 DMA Support .................................................................................................308
23.15 Register Description ......................................................................................309
23.16 Register Summary .........................................................................................315
23.17 Interrupt Vector Summary .............................................................................315
24 IRCOM - IR Communication Module .................................................. 316
24.1 Features ........................................................................................................316
24.2 Overview ........................................................................................................316
24.3 Registers Description ....................................................................................318
24.4 Register Summary .........................................................................................319