Datasheet

293
8331B–AVR–03/12
Atmel AVR XMEGA AU
23. USART
23.1 Features
• Full-duplex operation
• Asynchronous or synchronous operation
– Synchronous clock rates up to 1/2 of the device clock frequency
– Asynchronous clock rates up to 1/8 of the device clock frequency
• Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
• Fractional baud rate generator
– Can generate desired baud rate from any system clock frequency
– No need for external oscillator with certain frequencies
• Built-in error detection and correction schemes
– Odd or even parity generation and parity check
– Data overrun and framing error detection
– Noise filtering includes false start bit detection and digital low-pass filter
• Separate interrupts for
– Transmit complete
– Transmit data register empty
– Receive complete
• Multiprocessor communication mode
– Addressing scheme to address a specific devices on a multidevice bus
– Enable unaddressed devices to automatically ignore all frames
• Master SPI mode
– Double buffered operation
– Configurable data order
– Operation up to 1/2 of the peripheral clock frequency
• IRCOM module for IrDA compliant pulse modulation/demodulation
23.2 Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast
and flexible serial communication module. The USART supports full-duplex communication and
asynchronous and synchronous operation. The USART can be configured to operate in SPI
master mode and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide
range of standards. The USART is buffered in both directions, enabling continued data transmis-
sion without any delay between frames. Separate interrupts for receive and transmit complete
enable fully interrupt driven communication. Frame error and buffer overflow are detected in
hardware and indicated with separate status flags. Even or odd parity generation and parity
check can also be enabled.
A block diagram of the USART is shown in Figure 23-1 on page 294. The main functional blocks
are the clock generator, the transmitter, and the receiver, which are indicated in dashed boxes.