This document contains complete and detailed description of all modules included in the Atmel®AVR®XMEGA®AU microcontroller family. The Atmel AVR XMEGA AU is a family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture.
Atmel AVR XMEGA AU 1. About the Manual This document contains in-depth documentation of all peripherals and modules available for the Atmel AVR XMEGA AU microcontroller family. All features are documented on a functional level and described in a general sense. All peripherals and modules described in this manual may not be present in all Atmel AVR XMEGA AU devices.
Atmel AVR XMEGA AU 2. Overview The AVR XMEGA AU microcontrollers is a family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel AVR XMEGA AU devices achieve throughputs approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed.
Atmel AVR XMEGA AU The Atmel AVR XMEGA AU devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.Block Diagram Atmel AVR XMEGA AU block diagram. Oscillator / Crystal / Clock General Purpose I/O EBI VBAT Power Supervision 32.
Atmel AVR XMEGA AU In Table 2-1 on page 5 a feature summary for the XMEGA AU family is shown, split into one feature summary column for each sub-family. Each sub-family has identical feature set, but different memory options, refer to their device datasheet for ordering codes and memory options. Table 2-1. Feature XMEGA AU feature summary overview.
Atmel AVR XMEGA AU Feature Details / sub-family A1U A3U A3BU A4U USB full-speed device 1 1 1 1 USART 8 7 6 5 SPI 4 3 3 2 TWI 4 2 2 2 AES-128 Yes Yes Yes Yes DES Yes Yes Yes Yes CRC-16 Yes Yes Yes Yes CRC-32 Yes Yes Yes Yes 4 – – – 2 2 2 1 12 12 12 12 Sampling speed (kbps) 2000 2000 2000 2000 Input channels per ADC 16 16 16 12 Conversion channels 4 4 4 4 2 1 1 1 12 12 12 12 1000 1000 1000 1000 2 2 2 2 4 4 4 2 PDI Ye
Atmel AVR XMEGA AU 3. AVR CPU 3.1 Features • 8/16-bit, high-performance Atmel AVR RISC CPU • • • • • • • 3.
Atmel AVR XMEGA AU The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file.
Atmel AVR XMEGA AU 3.4.1 Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result.
Atmel AVR XMEGA AU Figure 3-3 on page 10 shows the internal timing concept for the register file. In a single clock cycle, an ALU operation using two register operands is executed and the result is stored back to the destination register. Figure 3-3. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 3.
Atmel AVR XMEGA AU The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction. To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts for up to four instructions or until the next I/O memory write. 3.9 Register File The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time.
Atmel AVR XMEGA AU Figure 3-5. Bit (individually) The X-, Y- and Z-registers. 7 7 15 Bit (individually) 7 XL R29 Y-register 8 7 0 7 0 15 Bit (individually) 7 YL R31 Z-register 0 R28 YH Bit (Y-register) 0 R26 XH Bit (X-register) Bit (Z-register) 0 R27 X-register 8 7 0 7 0 0 R30 ZH ZL 15 8 7 0 The lowest register address holds the least-significant byte (LSB), and the highest register address holds the most-significant byte (MSB).
Atmel AVR XMEGA AU 3.10.2 RAMPD Register This register is concatenated with the operand to enable direct addressing of the whole data memory space above 64KB. Together, RAMPD and the operand will form a 24-bit address. Figure 3-7. The combined RAMPD + K register. Bit (Individually) 7 0 15 0 RAMPD Bit (D-pointer) 3.10.
Atmel AVR XMEGA AU the fuses and signature row. This is handled globally by the configuration change protection (CCP) register. Changes to the protected I/O registers or bits, or execution of protected instructions, are only possible after the CPU writes a signature to the CCP register. The different signatures are described in the register description. There are two modes of operation: one for protected I/O registers, and one for the protected instructions, SPM/LPM. 3.12.
Atmel AVR XMEGA AU 3.14 3.14.1 Register Descriptions CCP – Configuration Change Protection register Bit 7 6 5 4 3 +0x04 2 1 0 CCP[7:0] CCP Read/Write W W W W W W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – CCP[7:0]: Configuration Change Protection The CCP register must be written with the correct signature to enable change of the protected I/O register or execution of the protected instruction for a maximum period of four CPU instruction cycles.
Atmel AVR XMEGA AU Bit 7 6 5 4 +0x09 3 2 1 0 RAMPX[7:0] RAMPX Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – RAMPX[7:0]: Extended X-pointer Address bits These bits hold the MSB of the 24-bit address created by RAMPX and the 16-bit X-register. Only the number of bits required to address the available data memory is implemented for each device. Unused bits will always read as zero. 3.14.
Atmel AVR XMEGA AU ECALL/EIJMP are used, and it will not be used if CALL and IJMP commands are used. For jump or call to addresses below 128KB, this register is not used. This register is not available if the program memory in the device is less than 128KB.
Atmel AVR XMEGA AU 3.14.9 SREG – Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. Bit 7 6 5 4 3 2 1 0 +0x0F I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set for interrupts to be enabled.
Atmel AVR XMEGA AU 3.
Atmel AVR XMEGA AU 4. Memories 4.
Atmel AVR XMEGA AU A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can only be written by an external programmer. 4.3 Flash Program Memory All XMEGA devices contain on-chip in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device.
Atmel AVR XMEGA AU application table section can be selected by the boot lock bits for this section. The possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. If this section is not used for data, application code can reside here. 4.3.
Atmel AVR XMEGA AU 4.5 Data Memory The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory, if available. The data memory is organized as one continuous memory section, as shown in Figure 4-2 on page 23. Figure 4-2. Data memory map.
Atmel AVR XMEGA AU 4.8 I/O Memory The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT instructions can address I/O memory locations in the range of 0x00 0x3F directly.
Atmel AVR XMEGA AU 4.10.1 Bus Priority When several masters request access to the same bus, the bus priority is in the following order (from higher to lower priority): 1. Bus Master with ongoing access. 2. Bus Master with ongoing burst. a. Alternating DMA controller read and DMA controller write when they access the same data memory section. 3. Bus Master requesting burst access. a. CPU has priority. 4. Bus Master requesting bus access. a. CPU has priority. 4.
Atmel AVR XMEGA AU 4.15 4.15.1 Register Description – NVM Controller ADDR0 – Address register 0 The ADDR0, ADDR1, and ADDR2 registers represent the 24-bit value ADDR. This is used for addressing all NVM sections for read, write, and CRC operations.
Atmel AVR XMEGA AU 4.15.5 DATA1 – Data register 1 Bit 7 6 5 4 +0x05 3 2 1 0 DATA[15:8] DATA1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – DATA[15:8]: Data Register Byte 1 This register gives the data value byte 1 when accessing NVM locations. 4.15.
Atmel AVR XMEGA AU • Bit 0 – CMDEX: Command Execute Setting this bit will execute the command in the CMD register. This bit is protected by the configuration change protection (CCP) mechanism. Refer to ”Configuration Change Protection” on page 13 for details on the CCP. 4.15.
Atmel AVR XMEGA AU • Bit 3:2 – SPMLVL[1:0]: SPM Ready Interrupt Level These bits enable the interrupt and select the interrupt level, as described in ”Interrupts and Programmable Multilevel Interrupt Controller” on page 134. This is a level interrupt that will be triggered only when the NVMBUSY flag in the STATUS register is set to zero. Thus, the interrupt should not be enabled before triggering an NVM command, as the NVMBUSY flag will not be set before the NVM command is triggered.
Atmel AVR XMEGA AU 4.15.12 LOCKBITS – Lock Bit register Bit 7 +0x07 6 5 BLBB[1:0] 4 3 BLBA[1:0] 2 1 BLBAT[1:0] 0 LB[1:0] LOCKBITS Read/Write R R R R R R R R Initial Value 1 1 1 1 1 1 1 1 This register is a mapping of the NVM lock bits into the I/O memory space, which enable direct read access from the application software. Refer to ”LOCKBITS – Lock Bit register” on page 35 for description.
Atmel AVR XMEGA AU 4.16 4.16.1 Register Descriptions – Fuses and Lock bits FUSEBYTE0 – Fuse Byte 0 Bit 7 6 5 4 +0x00 3 2 1 0 JTAGUID[7:0] FUSEBYTE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 • Bit 7 – JTAGUID[7:0]: JTAG USER ID These fuses can be used to set the default JTAG user ID for the device. During reset, the JTAGUID fuse bits will be loaded into the MCU JTAG user ID register. 4.16.
Atmel AVR XMEGA AU • Bit 6 – BOOTRST: Boot Loader Section Reset Vector This fuse can be programmed so the reset vector is pointing to the first address in the boot loader flash section. The device will then start executing from the boot loader flash section after reset. Table 4-1. Boot reset fuse. BOOTRST Reset Address 0 Reset vector = Boot loader reset 1 Reset vector = Application reset (address 0x0000) • Bit 5 – TOSCSEL: 32.
Atmel AVR XMEGA AU • Bit: 4 – RSTDISBL: External Reset Disable This fuse can be programmed to disable the external reset pin functionality. When this is done pulling the pin low will not cause an external reset. A reset is required before this bit will be read correctly after it is changed. • Bit 3:2 – STARTUPTIME[1:0]: Start-up time These fuse bits can be used to set at a programmable timeout period from all reset sources are released until the internal reset is released from the delay counter.
Atmel AVR XMEGA AU 4.16.5 FUSEBYTE5 – Fuse Byte 5 Bit 7 6 5 4 3 2 +0x05 – – BODACT[1:0] Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 1 1 – – – – – – EESAVE 1 0 BODLEVEL[2:0] FUSEBYTE5 • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to one when this register is written.
Atmel AVR XMEGA AU 4.16.6 LOCKBITS – Lock Bit register Bit 7 +0x07 6 5 BLBB[1:0] 4 3 BLBA[1:0] 2 1 BLBAT[1:0] 0 LB[1:0] LOCKBITS Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 • Bit 7:6 – BLBB[1:0]: Boot Lock Bit Boot Loader Section These lock bits control the software security level for accessing the boot loader section. The BLBB bits can only be written to a more strict locking.
Atmel AVR XMEGA AU Table 4-10. Boot lock bit for the application section. BLBA[1:0] Group Configuration 11 NOLOCK No Lock - no restrictions for SPM and (E)LPM accessing the application section. 10 WLOCK Write lock – SPM is not allowed to write the application section. RLOCK Read lock – (E)LPM executing from the boot loader section is not allowed to read from the application section.
Atmel AVR XMEGA AU bits is possible by executing a chip erase command. All other access; using the TIF and OCD, is blocked if any of the Lock Bits are written to 0. These bits do not block any software access to the memory. Table 4-12. Lock bit protection mode. LB[1:0] Group Configuration 11 NOLOCK3 10 WLOCK Write lock – programming of the flash and EEPROM is disabled for the programming interface. Fuse bits are locked for write from the programming interface.
Atmel AVR XMEGA AU 4.17.3 RCOSC32K – Internal 32.768kHz Oscillator Calibration register Bit 7 6 5 4 +0x02 3 2 1 0 RCOSC32K[7:0] RCOSC32K Read/Write R R R R R R R R Initial Value x x x x x x x x • Bit 7:0 – RCOSC32K[7:0]: Internal 32.768kHz Oscillator Calibration Value This byte contains the oscillator calibration value for the internal 32.768kHz oscillator. Calibration of the oscillator is performed during production test of the device.
Atmel AVR XMEGA AU Bit 7 6 5 4 +0x08 3 2 1 0 LOTNUM0[7:0] LOTNUM0 Read/Write R R R R R R R R Initial Value x x x x x x x x 2 1 0 • Bit 7:0 – LOTNUM0[7:0]: Lot Number Byte 0 This byte contains byte 0 of the lot number for the device. 4.17.
Atmel AVR XMEGA AU 4.17.10 LOTNUM4 – Lot Number register 4 Bit 7 6 5 4 +0x0C 3 2 1 0 LOTNUM4[7:0] LOTNUM4 Read/Write R R R R R R R R Initial Value x x x x x x x x 2 1 0 • Bit 7:0 – LOTNUM4[7:0]: Lot Number Byte 4 This byte contains byte 4 of the lot number for the device. 4.17.
Atmel AVR XMEGA AU 4.17.14 COORDX1 – Wafer Coordinate X register 1 Bit 7 6 5 4 +0x13 3 2 1 0 COORDX1[7:0] COORDX1 Read/Write R R R R R R R R Initial Value x x x x x x x x 2 1 0 • Bit 7:0 – COORDX0[7:0]: Wafer Coordinate X Byte 1 This byte contains byte 1 of wafer coordinate X for the device. 4.17.
Atmel AVR XMEGA AU 4.17.18 USBCAL1 – USB Pad Calibration register 1 Bit 7 6 5 4 +0x1B 3 2 1 0 USBCAL1[7:0] USBCAL1 Read/Write R R R R R R R R Initial Value x x x x x x x x • Bit 7:0 – USBCAL1[7:0]: USB Pad Calibration Register 1 This byte contains byte 1 of the USB pin calibration data, and must be loaded into the USB CALH register. 4.17.
Atmel AVR XMEGA AU • Bit 7:0 – ADCACAL1[7:0]: ADCA Calibration Byte 1 This byte contains byte 1 of the ADCA calibration data, and must be loaded into the ADCA CALH register. 4.17.22 ADCBCAL0 – ADCB Calibration register 0 ADCBCAL0 and ADCBCAL1 contains the calibration value for the analog to digital converter B(ADCB). Calibration is done during production test of the device. The calibration bytes are not loaded automatically into the ADC calibration registers, so this must be done from software.
Atmel AVR XMEGA AU 4.17.25 TEMPSENSE1 – Temperature Sensor Calibration register 1 Bit 7 6 5 4 +0x2F 3 2 1 0 TEMPSENSE1[7:0] TEMPSENSE1 Read/Write R R R R R R R R Initial Value 0 0 0 0 x x x x • Bit 7:0 – TEMPSENSE1[7:0]: Temperature Sensor Calibration Byte 1 This byte contains byte 1 of the temperature measurement. 4.17.
Atmel AVR XMEGA AU loaded automatically into the DAC channel 0 offset calibration register, so this must be done from software. 4.17.29 DACB0GAINCAL – DACB Gain Calibration register Bit 7 6 5 4 3 +0x33 2 1 0 DACB0GAINCAL[7:0] DACB0GAINCAL Read/Write R R R R R R R R Initial Value 0 0 0 0 x x x x • Bit 7:0 – DACB0GAINCAL[7:0]: DACB0 Gain Calibration Byte This byte contains the gain calibration value for channel 0 in the digital to analog converter B (DACB).
Atmel AVR XMEGA AU 4.17.32 DACB1OFFCAL – DACB Offset Calibration register Bit 7 6 5 4 3 +0x36 2 1 0 DACB1OFFCAL[7:0] DACB1OFFCAL Read/Write R R R R R R R R Initial Value 0 0 0 0 x x x x • Bit 7:0 – DACB1OFFCAL[7:0]: DACB1 Offset Calibration Byte This byte contains the offset calibration value for channel 1 in the digital to analog converter B (DACB). Calibration is done during production test of the device.
Atmel AVR XMEGA AU 4.20 4.20.1 Register Descriptions – MCU Control DEVID0 – Device ID register 0 DEVID0, DEVID1 and DEVID2 contain the byte identification that identifies each microcontroller device type. For details on the actual ID, refer to the device datasheet. Bit 7 6 5 4 3 2 1 0 Read/Write R R R R R R R R Initial Value 0 0 0 1 1 1 1 0 +0x00 DEVID0[7:0] DEVID0 • Bit 7:0 – DEVID0[7:0]: Device ID Byte 0 Byte 0 of the device ID. This byte will always be read as 0x1E.
Atmel AVR XMEGA AU • Bit 3:0 – REVID[3:0]: Revision ID These bits contains the device revision. 0 = A, 1= B and so on. 4.20.5 JTAGUID – JTAG User ID register Bit 7 6 5 4 Read/Write R R R R Initial Value 1/0 1/0 1/0 1/0 +0x04 3 2 1 0 R R R R 1/0 1/0 1/0 1/0 JTAGUID[7:0] JTAGUID • Bit 7:0 – JTAGUID[7:0]: JTAG User ID The JTAGUID can be used to identify two devices with identical device ID in a JTAG scan chain.
Atmel AVR XMEGA AU ule is enabled. This reduces the peak current consumption during startup of the module. For maximum effect the start-up delay should be set so that it is larger than 0.5µs. Table 4-13. 4.20.8 Analog startup delay.
Atmel AVR XMEGA AU • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 2 – AWEXELOCK: Advanced Waveform Extension Lock for TCE0 Setting this bit will lock all registers in the AWEXE module for timer/counter E0 for further modification. This bit is protected by the configuration change protection mechanism. For details refer to ”Configuration Change Protection” on page 13.
Atmel AVR XMEGA AU 4.
Atmel AVR XMEGA AU 4.
Atmel AVR XMEGA AU 4.
Atmel AVR XMEGA AU 5. DMAC - Direct Memory Access Controller 5.1 Features • Allows high speed data transfers with minimal CPU intervention • • • • • • • 5.
Atmel AVR XMEGA AU Figure 5-1. DMA Overview. DMA Channel 0 DMA trigger / Event CTRLA CTRLB TRIGSRC Enable Burst Control Logic TRFCNT REPCNT Arbitration R/W Master port Arbiter DESTADDR SRCADDR Read BUF Write DMA Channel 1 DMA Channel 2 Bus matrix CTRL DMA Channel 3 Slave port Read / Write 5.3 DMA Transaction A complete DMA read and write operation between memories and/or peripherals is called a DMA transaction.
Atmel AVR XMEGA AU Figure 5-2. DMA transaction. Four-byte burst mode Block size: 12 bytes Repeat count: 2 Burst transfer Block transfer DMA transaction 5.4 Transfer Triggers DMA transfers can be started only when a DMA transfer request is detected. A transfer request can be triggered from software, from an external trigger source (peripheral), or from an event. There are dedicated source trigger selections for each DMA channel.
Atmel AVR XMEGA AU one or more channels should have a fixed priority or if a round robin scheme should be used. A round robin scheme means that the channel that last transferred data will have the lowest priority. 5.7 Double Buffering To allow for continuous transfer, two channels can be interlinked so that the second takes over the transfer when the first is finished, and vice versa.
Atmel AVR XMEGA AU 5.12 Interrupts The DMA controller can generate interrupts when an error is detected on a DMA channel or when a transaction is complete for a DMA channel. Each DMA channel has a separate interrupt vector, and there are different interrupt flags for error and transaction complete. If repeat is not enabled, the transaction complete flag is set at the end of the block transfer. If unlimited repeat is enabled, the transaction complete flag is also set at the end of each block transfer.
Atmel AVR XMEGA AU 5.13 5.13.1 Register Description – DMA Controller CTRL – Control register Bit 7 6 5 4 3 ENABLE RESET – – DBUFMODE[1:0] Read/Write R/W R/W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x00 2 1 0 PRIMODE[1:0] CTRL • Bit 7 – ENABLE: Enable Setting this bit enables the DMA controller.
Atmel AVR XMEGA AU 5.13.2 INTFLAGS – Interrupt Status register Bit 7 6 5 4 3 2 1 0 CH3ERRIF CH2ERRIF CH1ERRIF CH0ERRIF CH3TRNFIF CH2TRNFIF CH1TRNFIF CH0TRNFIF Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x03 INTFLAGS • Bit 7:4 – CHnERRIF[3:0]: Channel n Error Interrupt Flag If an error condition is detected on DMA channel n, the CHnERRIF flag will be set. Writing a one to this bit location will clear the flag.
Atmel AVR XMEGA AU 5.13.5 TEMPH – Temporary Register High Bit 7 6 5 4 +0x07 3 2 1 0 TEMP[15:8] TEMPH Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – TEMP[15:8]: Temporary Register This register is used when reading and writing 24-bit registers in the DMA controller. Byte 2 of the 24-bit register is stored when it is written by the CPU. Byte 2 of the 24-bit register is stored here when byte 1 is read by the CPU.
Atmel AVR XMEGA AU • Bit 2 – SINGLE: Single-Shot Data transfer Setting this bit enables the single-shot mode. The channel will then do a burst transfer of BURSTLEN bytes on the transfer trigger. A write to this bit will be ignored while the channel is enabled. • Bit 1:0 – BURSTLEN[1:0]: Burst Mode These bits decide the DMA channel burst mode according to Table 5-3 on page 62. These bits cannot be changed if the channel is busy. Table 5-3. DMA channel burst mode.
Atmel AVR XMEGA AU 5.14.2 CTRLB – Control register B Bit 7 6 5 4 CHBUSY CHPEND ERRIF TRNIF Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x01 3 2 1 ERRINTLVL[1:0] 0 TRNINTLVL[1:0] CTRLB • Bit 7 – CHBUSY: Channel Busy When the DMA channel starts a DMA transaction, the CHBUSY flag will be read as one.
Atmel AVR XMEGA AU • Bit 7:6 – SRCRELOAD[1:0]: Channel Source Address Reload These bits decide the DMA channel source address reload according to Table 5-5. A write to these bits is ignored while the channel is busy. Table 5-5. DMA channel source address reload settings. SRCRELOAD[1:0] Group Configuration Description 00 NONE No reload performed. 01 BLOCK DMA source address register is reloaded with initial value at end of each block transfer.
Atmel AVR XMEGA AU Table 5-8. 5.14.4 DMA channel destination address mode settings.
Atmel AVR XMEGA AU Table 5-9. DMA trigger source base values for all modules and peripherals.
Atmel AVR XMEGA AU Table 5-12. DMA trigger source offset values for timer/ counter triggers. TRGSRC Offset Value Group Configuration +0x00 OVF Overflow/underflow +0x01 ERR Error +0x02 CCA Compare or capture channel A +0x03 CCB Compare or capture channel B +0x04 Note: (1) Compare or capture channel C (1) Compare or capture channel D CCC +0x05 Description CCD 1. CC channel C and D triggers are available only for timer/counters 0. Table 5-13.
Atmel AVR XMEGA AU • Bit 7:0 – TRFCNT[15:8]: Channel n Block Transfer Count register High These bits hold the MSB of the 16-bit block transfer count. The default value of this register is 0x1. If a user writes 0x0 to this register and fires a DMA trigger, DMA will be doing 0xFFFF transfers. 5.14.
Atmel AVR XMEGA AU 5.14.10 SRCADDR2 – Channel Source Address 2 Reading and writing 24-bit values require special attention. For details, refer to ”Accessing 24and 32-bit Registers” on page 13. Bit 7 6 5 +0x0A 4 3 2 1 0 SRCADDR[23:16] SRCADDR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – SRCADDR[23:16]: Channel Source Address 2 These bits hold byte 2 of the 24-bit source address. 5.14.
Atmel AVR XMEGA AU 5.
Atmel AVR XMEGA AU 6. Event System 6.1 Features • System for direct peripheral-to-peripheral communication and signaling • Peripherals can directly send, receive, and react to peripheral events • • • • 6.
Atmel AVR XMEGA AU Figure 6-1. Event system overview and connected peripherals. CPU / Software DMA Controller Event Routing Network ADC AC clkPER Prescaler Real Time Counter Event System Controller Timer / Counters DAC USB Port pins IRCOM The event routing network consists of eight software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to eight parallel event configurations and routings.
Atmel AVR XMEGA AU Figure 6-2. Example of event source, generator, user, and action. Event Generator Event User Timer/Counter ADC Compare Match Over-/Underflow | Event Routing Network Error Channel Sweep Single Conversion Event Action Selection Event Source Event Action Events can also be generated manually in software. 6.3.1 Signaling Events Signaling events are the most basic type of event.
Atmel AVR XMEGA AU Software-generated events last for one clock cycle and will overwrite events from other event generators on that event channel during that clock cycle. Table 6-1 on page 74 shows the different events, how they can be manually generated, and how they are decoded. Table 6-1. 6.4 Manually generated events and decoding of events.
Atmel AVR XMEGA AU Figure 6-3. Event routing network.
Atmel AVR XMEGA AU 6.5 Event Timing An event normally lasts for one peripheral clock cycle, but some event sources, such as a low level on an I/O pin, will generate events continuously. Details on this are described in the datasheet for each peripheral, but unless otherwise stated, an event lasts for one peripheral clock cycle. It takes a maximum of two peripheral clock cycles from when an event is generated until the event actions in other peripherals are triggered.
Atmel AVR XMEGA AU Figure 6-4. Quadrature signals from a rotary encoder. 1 cycle / 4 states Forward Direction QDPH0 QDPH90 QDINDX 00 10 11 01 01 11 10 00 Backward Direction QDPH0 QDPH90 QDINDX Figure 6-4 shows typical quadrature signals from a rotary encoder. The signals QDPH0 and QDPH90 are the two quadrature signals. When QDPH90 leads QDPH0, the rotation is defined as positive or forward. When QDPH0 leads QDPH90, the rotation is defined as negative or reverse.
Atmel AVR XMEGA AU • Set the period register of the timer/counter to ('line count' * 4 - 1), the line count of the quadrature encoder. • Enable the timer/counter without clock prescaling. The angle of a quadrature encoder attached to QDPH0, QDPH90 (and QINDX) can now be read directly from the timer/counter count register. If the count register is different from BOTTOM when the index is recognized, the timer/counter error flag is set.
Atmel AVR XMEGA AU Table 6-3. CHnMUX[7:0] bit settings.
Atmel AVR XMEGA AU Table 6-4. 6.8.2 Timer/counter events.
Atmel AVR XMEGA AU Table 6-6. Digital filter coefficient values . DIGFILT[2:0] 6.8.
Atmel AVR XMEGA AU 6.
Atmel AVR XMEGA AU 7. System Clock and Clock Options 7.1 Features • Fast start-up time • Safe run-time clock switching • Internal oscillators: • • • • • • 7.2 – 32MHz run-time calibrated oscillator – 2MHz run-time calibrated oscillator – 32.768kHz calibrated oscillator – 32kHz ultra low power (ULP) oscillator with 1kHz output External clock options – 0.4MHz - 16MHz crystal oscillator – 32.
Atmel AVR XMEGA AU Figure 7-1. The clock system, clock sources, and clock distribution. Real Time Counter RAM Peripherals AVR CPU Non-Volatile Memory clkPER clkCPU clkPER2 clkPER4 USB clkUSB Brown-out Detector System Clock Prescalers Watchdog Timer Prescaler clkSYS clkRTC System Clock Multiplexer (SCLKSEL) RTCSRC USBSRC DIV32 DIV32 DIV32 PLL PLLSRC DIV4 XOSCSEL 32 kHz Int. ULP 32.768 kHz Int. OSC 32.768 kHz TOSC 0.4 – 16 MHz XTAL 32 MHz Int. Osc 2 MHz Int.
Atmel AVR XMEGA AU 7.3 Clock Distribution Figure 7-1 on page 84 presents the principal clock distribution system used in XMEGA devices. 7.3.1 System Clock - ClkSYS The system clock is the output from the main system clock selection. This is fed into the prescalers that are used to generate all internal clocks except the asynchronous and USB clocks. 7.3.2 CPU Clock - ClkCPU The CPU clock is routed to the CPU and nonvolatile memory. Halting the CPU clock inhibits the CPU from executing instructions. 7.
Atmel AVR XMEGA AU 7.4.1.2 32.768kHz Calibrated Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz output. 7.4.1.
Atmel AVR XMEGA AU Figure 7-3. 7.4.2.3 External clock drive configuration. General Purpose I/O XTAL2 External Clock Signal XTAL1 32.768kHz Crystal Oscillator A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A typical connection is shown in Figure 7-4 on page 87. A low power mode with reduced voltage swing on TOSC2 is available.
Atmel AVR XMEGA AU Figure 7-5. System clock selection and prescalers. Clock Selection Internal 32.768kHz Osc. ClkPER4 Internal 2MHz Osc. ClkPER2 ClkCPU Internal 32MHz Osc. Internal PLL. ClkSYS Prescaler A 1, 2, 4, ... , 512 Prescaler B 1, 2, 4 Prescaler C 1, 2 ClkPER External Oscillator or Clock. Prescaler A divides the system clock, and the resulting clock is clkPER4.
Atmel AVR XMEGA AU 7.7 DFLL 2MHz and DFLL 32MHz Two built-in digital frequency locked loops (DFLLs) can be used to improve the accuracy of the 2MHz and 32MHz internal oscillators. The DFLL compares the oscillator frequency with a more accurate reference clock to do automatic run-time calibration of the oscillator and compensate for temperature and voltage drift. The choices for the reference clock sources are: • 32.768kHz calibrated internal oscillator • 32.
Atmel AVR XMEGA AU The value that should be written to the COMP register is given by the following formula: COMP = hex ( f OSC f RCnCREF ) When the DFLL is enabled, it controls the ratio between the reference clock frequency and the oscillator frequency. If the internal oscillator runs too fast or too slow, the DFLL will decrement or increment its calibration register value by one to adjust the oscillator frequency.
Atmel AVR XMEGA AU • Issue a non-maskable interrupt (NMI) If the PLL or external clock source fails when not being used for the system clock, it is automatically disabled, and the system clock will continue to operate normally. No NMI is issued. The failure monitor is meant for external clock sources above 32kHz. It cannot be used for slower external clocks. When the failure monitor is enabled, it will not be disabled until the next reset.
Atmel AVR XMEGA AU 7.9 7.9.1 Register Description – Clock CTRL – Control register Bit 7 6 5 4 3 +0x00 – – – – – 2 1 0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SCLKSEL[2:0] CTRL • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU • Bit 6:2 – PSADIV[4:0]: Prescaler A Division Factor These bits define the division ratio of the clock prescaler A according to Table 7-2. These bits can be written at run-time to change the frequency of the ClkPER4 clock relative to the system clock, ClkSYS. Table 7-2. Prescaler A division factor.
Atmel AVR XMEGA AU 7.9.3 LOCK – Lock register Bit 7 6 5 4 3 2 1 0 +0x02 – – – – – – – LOCK Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 LOCK • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU • Bit 0 – RTCEN: RTC Clock Source Enable Setting the RTCEN bit enables the selected RTC clock source for the real-time counter. 7.9.5 USBSCTRL – USB Control register Bit 7 6 5 4 3 2 +0x04 – – Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 USBPSDIV[2:0] 1 USBSRC[1:0] 0 USBSEN USBSCTRL • Bit 7:6 – Reserved These bits are unused and reserved for future use.
Atmel AVR XMEGA AU 7.10 Register Description – Oscillator 7.10.1 CTRL – Oscillator Control register Bit 7 6 5 4 3 2 1 0 +0x00 – – – PLLEN XOSCEN RC32KEN RC32MEN RC2MEN Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 1 CTRL • Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU 7.10.2 STATUS – Oscillator Status register Bit 7 6 5 4 3 2 1 0 +0x01 – – – PLLRDY XOSCRDY RC32KRDY RC32MRDY RC2MRDY Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 STATUS • Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU Table 7-7. 16MHz crystal oscillator frequency range selection. Typical Frequency Range Recommended Range for Capacitors C1 and C2 (pF) FRQRANGE[1:0] Group Configuration 00 04TO2 0.4MHz - 2MHz 100-300 01 2TO9 2MHz - 9MHz 10-40 10 9TO12 9MHz - 12MHz 10-40 11 12TO16 12MHz - 16MHz 10-30 Note: Refer to Electrical characteristics section in device datasheet to retrieve the best setting for a given frequency. • Bit 5 – X32KLPM: Crystal Oscillator 32.
Atmel AVR XMEGA AU 7.10.4 XOSCFAIL – XOSC Failure Detection register Bit 7 6 5 4 3 2 1 0 +0x03 – – – – PLLFDIF PLLFDEN XOSCFDIF XOSCFDEN Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 XOSCFAIL • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU 7.10.6 PLLCTRL – PLL Control register Bit 7 +0x05 6 5 PLLSRC[1:0] 4 3 PLLDIV 2 1 0 PLLFAC[4:0] PLLCTRL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:6 – PLLSRC[1:0]: Clock Source The PLLSRC bits select the input source for the PLL according to Table 7-9 on page 100. Table 7-9.
Atmel AVR XMEGA AU Table 7-10. 32MHz oscillator reference selection. RC32MCREF[1:0] Group Configuration Description 00 RC32K 01 XOSC32 32.768kHz crystal oscillator on TOSC 10 USBSOF USB start of frame 11 — 32.768kHz internal oscillator Reserved • Bit 0 – RC2MCREF: 2MHz Oscillator Calibration Reference This bit is used to select the calibration source for the 2MHz DFLL. By default, this bit is zero and the 32.768kHz internal oscillator is selected. If this bit is set to one, the 32.
Atmel AVR XMEGA AU • Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 6:0 – CALA[6:0]: DFLL Calibration Bits These bits hold the part of the oscillator calibration value that is used for automatic runtime calibration.
Atmel AVR XMEGA AU 7.11.5 COMP2 – DFLL Compare register Byte 2 Bit 7 6 5 4 +0x06 3 2 1 0 COMP[15:8] COMP2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – COMP2[15:8]: Compare Register Byte 2 These bits hold byte 2 of the 16-bit compare register. Table 7-11. Nominal DFLL32M COMP values for different output frequencies. Oscillator Frequency (MHz) COMP Value (ClkRCnCREF = 1.024kHz) 30.0 0x7270 32.0 0x7A12 34.0 0x81B3 36.
Atmel AVR XMEGA AU 7.12 Register Summary - Clock Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 +0x00 CTRL – – – – – +0x01 PSCTRL – +0x02 LOCK – – – +0x03 RTCCTRL – – – +0x04 USBSCTRL – – +0x05 Reserved – – – – – – – – +0x06 Reserved – – – – – – – – +0x07 Reserved – – – – – – – – 7.
Atmel AVR XMEGA AU 8. Power Management and Sleep Modes 8.1 Features • Power management for adjusting power consumption and functions • Five sleep modes – Idle – Power down – Power save – Standby – Extended standby • Power reduction register to disable clock and turn off unused peripherals in active and idle modes 8.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
Atmel AVR XMEGA AU Table 8-1 on page 106 shows the different sleep modes and the active clock domains, oscillators, and wake-up sources. Active clock domains and wake-up sources in the different sleep modes.
Atmel AVR XMEGA AU 8.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 8.3.5 8.4 Extended Standby Mode Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
Atmel AVR XMEGA AU 8.5.4 Watchdog Timer If the watchdog timer is not needed in the application, the module should be turned off. If the watchdog timer is enabled, it will be enabled in all sleep modes and, hence, always consume power. Refer to ”WDT – Watchdog Timer” on page 128 for details on how to configure the watchdog timer. 8.5.5 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. Most important is to ensure that no pins drive resistive loads.
Atmel AVR XMEGA AU 8.6 8.6.1 Register Description – Sleep CTRL – Control register Bit 7 6 5 4 3 2 1 +0x00 – – – – Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMODE[2:0] 0 SEN CTRL • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU • Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 6 – USB: USB Module Setting this bit stops the clock to the USB module. When this bit is cleared, the peripheral should be reinitialized to ensure proper operation. • Bit 5 – Reserved This bit is unused and reserved for future use.
Atmel AVR XMEGA AU • Bit 1 – ADC: Power Reduction ADC Setting this bit stops the clock to the ADC. The ADC should be disabled before stopped. • Bit 0 – AC: Power Reduction Analog Comparator Setting this bit stops the clock to the analog comparator. The AC should be disabled before shutdown. 8.7.
Atmel AVR XMEGA AU 8.8 Register Summary – Sleep Address +0x00 8.
Atmel AVR XMEGA AU 9. Reset System 9.1 Features • Reset the microcontroller and set it to initial state when a reset source goes active • Multiple reset sources that cover different situations – Power-on reset – External reset – Watchdog reset – Brownout reset – PDI reset – Software reset • Asynchronous operation – No running system clock in the device is required for reset • Reset status register for reading the reset source from the application code 9.
Atmel AVR XMEGA AU Figure 9-1. Reset system overview. Power-on Reset BODLEVEL [2:0] PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Brown-out Reset Pull-up Resistor SPIKE FILTER External Reset PDI Reset Software Reset Watchdog Reset ULP Oscillator Delay Counters TIMEOUT SUT[1:0] 9.3 Reset Sequence A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active.
Atmel AVR XMEGA AU Whenever a reset occurs, the clock system is reset and the internal 2MHz internal oscillator is chosen as the source for ClkSYS. 9.3.2 9.4 9.4.1 Oscillator Startup After the reset delay, the 2MHz internal oscillator clock is started, and its calibration values are automatically loaded from the calibration row to the calibration registers. Reset Sources Power-on Reset A power-on reset (POR) is generated by an on-chip detection circuit.
Atmel AVR XMEGA AU When the BOD is enabled and VCC decreases to a value below the trigger level (VBOT- in Figure 9-4), the brownout reset is immediately activated. When VCC increases above the trigger level (VBOT+ in Figure 9-4), the reset counter starts the MCU after the timeout period, tTOUT, has expired. The trigger level has a hysteresis to ensure spike free brownout detection. The hysteresis on the detection level should be interpreted as VBOT+= VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
Atmel AVR XMEGA AU • Enabled: In this mode, the VCC level is continuously monitored, and a drop in VCC below VBOT for a period of tBOD will give a brownout reset • Sampled: In this mode, the BOD circuit will sample the VCC level with a period identical to that of the 1kHz output from the ultra low power (ULP) internal oscillator. Between each sample, the BOD is turned off.
Atmel AVR XMEGA AU Figure 9-6. Watchdog reset. CC 1-2 2MHz Cycles For information on configuration and use of the WDT, refer to the ”WDT – Watchdog Timer” on page 128. 9.4.5 Software Reset The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset control register.The reset will be issued within two CPU clock cycles after writing the bit.
Atmel AVR XMEGA AU 9.5 9.5.1 Register Description STATUS – Status register Bit 7 6 5 4 3 2 1 0 +0x00 – – SRF PDIRF WDRF BORF EXTRF PORF Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value - - - - - - - - STATUS • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 5 – SRF: Software Reset Flag This flag is set if a software reset occurs.
Atmel AVR XMEGA AU 9.
Atmel AVR XMEGA AU 10. Battery Backup System 10.1 Features • Integrated battery backup system ensuring continuos, real-time clock during main power failure • Battery backup power supply from dedicated VBAT pin to power: – One 32-bit real-time counter – One ultra low power 32.
Atmel AVR XMEGA AU 10.3 Battery Backup System The battery backup system consists of a VBAT power supervisor, a power switch, a crystal oscillator with failure monitor, a 32-bit real-time counter (RTC), and two backup registers. Figure 10-1. Battery backup system and its power domain implementation.
Atmel AVR XMEGA AU 10.3.3 Crystal Oscillator with Failure Monitor The crystal oscillator (XOSC) supports connection of a external 32.768kHz crystal. It provides a prescaled clock output selectable to 1.024kHz or 1Hz. The crystal oscillator is designed for ultra low power consumption and by default is configured for low ESR and load capacitance crystals. It is possible to enable a high ESR mode to drive crystals with high ESR or load capacitance, but this will increase current consumption.
Atmel AVR XMEGA AU 10.5.2 Main Power Restore and Start-up Sequence At every startup after main power is restored, the software should: 1. Control the main reset source to determine that a POR or BOD took place. 2. Check for power on the VBAT pin by reading the BBPWR flag. 3. Read the power supervisor flags to determine further software action: a. If all power supervision flags are cleared, the battery backup system runs as normal.
Atmel AVR XMEGA AU 10.6 10.6.1 Register Description CTRL: Control register Bit 7 6 5 4 3 2 1 0 +0x00 – – HIGHESR XOSCSEL XOSCEN XOSCFDEN ACCEN RESET Read/Write R R R/W R/W R/W R/W R/W R/W initial Value 0 0 0 0 0 0 0 0 CTRL • Bit 7: 6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written.
Atmel AVR XMEGA AU This bit is protected by the Configuration Change Protection mechanism. For a detailed description, refer to ”Configuration Change Protection” on page 13. 10.6.2 STATUS: Status register Bit 7 6 5 4 3 2 1 0 BBPWR – – – XOSCRDY XOSCFAIL BBBODF BBPODF Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 x x 0 0 +0x01 STATUS • Bit 7 – BBPWR: Battery Backup Power This flag is set if no power is detected on the VBAT pin when the device leaves reset.
Atmel AVR XMEGA AU • Bit 7:0 – BACKUP0[7:0]: Backup Register 0 This register can be used to store data in the battery backup system before the main power is lost or removed. 10.6.
Atmel AVR XMEGA AU 11. WDT – Watchdog Timer 11.1 Features • • • • • Issues a device reset if the timer is not reset before its timeout period Asynchronous operation from dedicated oscillator 1kHz output of the 32kHz ultra low power oscillator 11 selectable timeout periods, from 8ms to 8s. Two operation modes: – Normal mode – Window mode • Configuration lock to prevent unwanted changes 11.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation.
Atmel AVR XMEGA AU Figure 11-1. Normal mode operation. 11.4 Window Mode Operation In window mode operation, the WDT uses two different timeout periods, a "closed" window timeout period (TOWDTW) and the normal timeout period (TOWDT). The closed window timeout period defines a duration of from 8ms to 8s where the WDT cannot be reset. If the WDT is reset during this period, the WDT will issue a system reset.
Atmel AVR XMEGA AU 11.6 Configuration Protection and Lock The WDT is designed with two security mechanisms to avoid unintentional changes to the WDT settings. The first mechanism is the configuration change protection mechanism, employing a timed write procedure for changing the WDT control registers. In addition, for the new configuration to be written to the control registers, the register’s change enable bit must be written at the same time.
Atmel AVR XMEGA AU Table 11-1. Watchdog timeout periods (Continued). PER[3:0] Group Configuration Typical Timeout Periods 0110 512CLK 0.512s 0111 1KCLK 1.0s 1000 2KCLK 2.0s 1001 4KCLK 4.0s 1010 8KCLK 8.0s 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Note: Reserved settings will not give any timeout. • Bit 1 – ENABLE: Enable This bit enables the WDT. Clearing this bit disables the watchdog timer.
Atmel AVR XMEGA AU The initial values of these bits are set by the watchdog window timeout period (WDWP) fuses, and are loaded at power-on. In normal mode these bits are not in use. In order to change these bits, the WCEN bit must be written to one at the same time. These bits are protected by the configuration change protection mechanism. For a detailed description, refer to ”Configuration Change Protection” on page 13. Table 11-2.
Atmel AVR XMEGA AU 11.7.3 STATUS – Status register Bit 7 6 5 4 3 2 1 0 +0x02 – – – – – – – SYNCBUSY Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 STATUS • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU 12. Interrupts and Programmable Multilevel Interrupt Controller 12.
Atmel AVR XMEGA AU request. The RET (subroutine return) instruction cannot be used when returning from the interrupt handler routine, as this will not return the PMIC to its correct state. Figure 12-1. Interrupt controller overview Interrupt Controller Priority decoder INT LEVEL Peripheral 1 INT REQ INT ACK CPU ”RETI” CPU INT ACK INT LEVEL Peripheral n INT REQ INT ACK CPU INT LEVEL CPU INT REQ INT REQ INT ACK LEVEL Enable CTRL 12.4 STATUS INTPRI Global Interrupt Enable CPU.
Atmel AVR XMEGA AU 12.4.1 NMI – Non-Maskable Interrupts Which interrupts represent NMI and which represent regular interrupts cannot be selected. Nonmaskable interrupts must be enabled before they can be used. Refer to the device datasheet for NMI present on each device. An NMI will be executed regardless of the setting of the I bit, and it will never change the I bit. No other interrupts can interrupt a NMI handler.
Atmel AVR XMEGA AU Figure 12-2. Interrupt execution of a multicycle instruction. If an interrupt occurs when the device is in sleep mode, the interrupt execution response time is increased by five clock cycles. In addition, the response time is increased by the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four to five clock cycles, depending on the size of the program counter.
Atmel AVR XMEGA AU 12.5 Interrupt level The interrupt level is independently selected for each interrupt source. For any interrupt request, the PMIC also receives the interrupt level for the interrupt. The interrupt levels and their corresponding bit values for the interrupt level configuration of all interrupts is shown in Table 12-1. Table 12-1. Interrupt levels. Interrupt Level Configuration Group Configuration 00 OFF Interrupt disabled.
Atmel AVR XMEGA AU Figure 12-3. Static priority. Lowes t Addres s IVEC 0 Highes t Priority : : : IVEC x IVEC x+1 : : : Highes t Addres s 12.6.2 IVEC N Lowes t Priority Round-robin Scheduling To avoid the possible starvation problem for low-level interrupts with static priority, where some interrupts might never be served, the PMIC offers round-robin scheduling for low-level interrupts.
Atmel AVR XMEGA AU 12.7 Interrupt vector locations Table 12-2 on page 140 shows reset and Interrupt vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 12-2.
Atmel AVR XMEGA AU 12.8 12.8.1 Register Description STATUS – Status register Bit 7 6 5 4 3 2 1 0 NMIEX – – – – HILVLEX MEDLVLEX LOLVLEX Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 +0x00 STATUS • Bit 7 – NMIEX: Non-Maskable Interrupt Executing This flag is set if a non-maskable interrupt is executing. The flag will be cleared when returning (RETI) from the interrupt handler. • Bit 6:3 – Reserved These bits are unused and reserved for future use.
Atmel AVR XMEGA AU 12.8.3 CTRL – Control register Bit 7 6 5 4 3 2 1 0 RREN IVSEL – – – HILVLEN MEDLVLEN LOLVLEN Read/Write R/W R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x02 CTRL • Bit 7 – RREN: Round-robin Scheduling Enable When the RREN bit is set, the round-robin scheduling scheme is enabled for low-level interrupts. When this bit is cleared, the priority is static according to interrupt vector address, where the lowest address has the highest priority.
Atmel AVR XMEGA AU 13. I/O Ports 13.1 Features • General purpose input and output pins with individual configuration • Output driver with configurable driver and pull settings: • • • • • • • • • • 13.
Atmel AVR XMEGA AU Figure 13-1 on page 144 shows the I/O pin functionality and the registers that are available for controlling a pin. Figure 13-1. General I/O pin functionality. Pull Enable C o n t r o l PINnCTRL Q D R L o g i c Pull Keep Pull Direction Input Disable Wired AND/OR Slew Rate Limit Inverted I/O OUTn Pxn Q D R DIRn Q D R Synchronizer INn Q D R Q D R Digital Input Pin Analog Input/Output 13.
Atmel AVR XMEGA AU The pin n configuration (PINnCTRL) register is used for additional I/O pin configuration. A pin can be set in a totem-pole, wired-AND, or wired-OR configuration. It is also possible to enable inverted input and output for a pin. A totem-pole output has four possible pull configurations: totem-pole (push-pull), pull-down, pullup, and bus-keeper. The bus-keeper is active in both directions. This is to avoid oscillation when disabling the output.
Atmel AVR XMEGA AU 13.3.1.2 Totem-pole with Pull-up In this mode, the configuration is as for totem-pole, expect the pin is configured with internal pullup when set as input. Figure 13-4. I/O pin configuration - Totem-pole with pull-up (on input). DIRn OUTn Pn INn 13.3.2 Bus-keeper In the bus-keeper configuration, it provides a weak bus-keeper that will keep the pin at its logic level when the pin is no longer driven to high or low.
Atmel AVR XMEGA AU Figure 13-6. Output configuration - Wired-OR with optional pull-down. OUTn Pn INn 13.3.4 Wired-AND In the wired-AND configuration, the pin will be driven low when the corresponding bits in the OUT and DIR registers are written to zero. When the OUT register is set to one, the pin is released allowing the pin to be pulled high with the internal or an external pull-resistor. If internal pull-up is used, this is also active if the pin is set as input. Figure 13-7.
Atmel AVR XMEGA AU Figure 13-8. Synchronization when reading a pin value. PERIPHERAL CLK INSTRUCTIONS xxx xxx lds r17, PORTx+IN SYNCHRONIZER FLIPFLOP IN r17 0x00 0xFF tpd, max tpd, min 13.5 Input Sense Configuration Input sensing is used to detect an edge or level on the I/O pin input. The different sense configurations that are available for each pin are detection of a rising edge, falling edge, or any edge or detection of a low level.
Atmel AVR XMEGA AU 13.6 Port Interrupt Each port has two interrupt vectors, and it is configurable which pins on the port will trigger each interrupt. Port interrupts must be enabled before they can be used. Which sense configurations can be used to generate interrupts is dependent on whether synchronous or asynchronous input sensing is available for the selected pin. For synchronous sensing, all sense configurations can be used to generate interrupts.
Atmel AVR XMEGA AU Table 13-3. Limited asynchronous sense support. Sense Settings 13.7 Supported Interrupt Description Rising edge No - Falling edge No - Any edge Yes Pin value must be kept unchanged during wake up Low level Yes Pin level must be kept unchanged during wake up Port Event Port pins can generate an event when there is a change on the pin. The sense configurations decide the conditions for each pin to generate events.
Atmel AVR XMEGA AU Figure 13-10. Port override signals and related logic. Pull Enable PINnCTRL Q D C o n t r o l Pull Keep L o g i c Digital Input Disable (DID) Pull Direction R DID Override Value DID Override Enable Wired AND/OR Slew Rate Limit Inverted I/O OUTn Pxn Q D OUT Override Value R OUT Override Enable DIRn Q D DIR Override Value R DIR Override Enable Synchronizer INn Q D R Q D R Digital Input Pin Analog Input/Output 13.
Atmel AVR XMEGA AU 13.11 Multi-pin configuration The multi-pin configuration function is used to configure multiple port pins using a single write operation to only one of the port pin configuration registers. A mask register decides which port pin is configured when one port pin register is written, while avoiding several pins being written the same way during identical write operations. 13.
Atmel AVR XMEGA AU 13.13 Register Descriptions – Ports 13.13.1 DIR – Data Direction register Bit 7 6 5 4 3 +0x00 2 1 0 DIR[7:0] DIR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – DIR[7:0]: Data Direction This register sets the data direction for the individual pins of the port. If DIRn is written to one, pin n is configured as an output pin. If DIRn is written to zero, pin n is configured as an input pin. 13.13.
Atmel AVR XMEGA AU • Bit 7:0 – DIRTGL[7:0]: Port Data Direction Toggle This register can be used instead of a read-modify-write to toggle the direction of individual pins. Writing a one to a bit will toggle the corresponding bit in the DIR register. Reading this register will return the value of the DIR register. 13.13.
Atmel AVR XMEGA AU 13.13.8 OUTTGL – Data Output Value Toggle register Bit 7 6 5 4 +0x07 3 2 1 0 OUTTGL[7:0] OUTTGL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – OUTTGL[7:0]: Port Data Output Value Toggle This register can be used instead of a read-modify-write to toggle the output value of individual pins. Writing a one to a bit will toggle the corresponding bit in the OUT register.
Atmel AVR XMEGA AU • Bit 7:0 – INT0MSK[7:0]: Interrupt 0 Mask Register These bits are used to mask which pins can be used as sources for port interrupt 0. If INT0MASKn is written to one, pin n is used as source for port interrupt 0.The input sense configuration for each pin is decided by the PINnCTRL registers. 13.13.
Atmel AVR XMEGA AU • Bit 4 – USART0: USART0 Remap Setting this bit to one will move the pin location of USART0 from Px[3:0] to Px[7:4]. • Bit 3 – TC0D: Timer/Counter 0 Output Compare D Setting this bit will move the location of OC0D from Px3 to Px7. • Bit 2 – TC0C: Timer/Counter 0 Output Compare C Setting this bit will move the location of OC0C from Px2 to Px6. • Bit 1 – TC0B: Timer/Counter 0 Output Compare B Setting this bit will move the location of OC0B from Px1 to Px5.
Atmel AVR XMEGA AU Table 13-5. Output/pull configuration.
Atmel AVR XMEGA AU 13.14 Register Descriptions – Port Configuration 13.14.1 MPCMASK – Multi-pin Configuration Mask register Bit 7 6 5 +0x00 4 3 2 1 0 MPCMASK[7:0] MPCMASK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – MPCMASK[7:0]: Multi-pin Configuration Mask The MPCMASK register enables configuration of several pins of a port at the same time. Writing a one to bit n makes pin n part of the multi-pin configuration.
Atmel AVR XMEGA AU • Bit 3:0 – VP2MAP: Virtual Port 2 Mapping These bits decide which ports should be mapped to Virtual Port 2. The registers DIR, OUT, IN, and INTFLAGS will be mapped. Accessing the virtual port registers is equal to accessing the actual port registers. See Table 13-7 for configuration. Table 13-7. Virtual port mapping. VPnMAP[3:0] 13.14.
Atmel AVR XMEGA AU Table 13-8 on page 161 shows the possible configurations. Table 13-8. Event output pin selection. EVOUT[1:0] Group Configuration Description 00 OFF 01 PC Event channel 0 output on PORTC 10 PD Event channel 0 output on PORTD 11 PE Event channel 0 output on PORTE Event output disabled • Bits 3:2 – CLKOUTSEL[1:0] : Clock Output Select These bits are used to select which of the peripheral clocks will be output to the port pin if CLKOUT is configured. Table 13-9.
Atmel AVR XMEGA AU • Bit 3:2 – EBIADROUT[1:0]: EBI Address Output The maximum configuration of the external bus interface (EBI) requires up to 32 dedicated pins. For devices with only 24 EBI pins available, eight additional pins can be enabled and placed on alternate pin locations in order to get a full 32-pin EBI. The port pins must be configured as output for signals to be available on the pins. These bits are available on devices with only three ports dedicated for the EBI interface.
Atmel AVR XMEGA AU Table 13-14. Event channel output selection.
Atmel AVR XMEGA AU 13.15 Register Descriptions – Virtual Port 13.15.1 DIR – Data Direction Bit 7 6 5 4 +0x00 3 2 1 0 DIR[7:0] DIR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – DIR[7:0]: Data Direction Register This register sets the data direction for the individual pins in the port mapped by VPCTRLA, virtual port-map control register A or VPCTRLB, virtual port-map control register B.
Atmel AVR XMEGA AU 13.15.4 INTFLAGS – Interrupt Flag register Bit 7 6 5 4 3 2 1 0 +0x03 – – – – – – INT1IF INT0IF Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 INTFLAGS • Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU 13.
Atmel AVR XMEGA AU 13.19 Interrupt Vector Summary – Ports Table 13-15. Port interrupt vectors and their word offset address.
Atmel AVR XMEGA AU 14. TC0/1 – 16-bit Timer/Counter Type 0 and 1 14.1 Features • 16-bit timer/counter • 32-bit timer/counter support by cascading two timer/counters • Up to four compare or capture (CC) channels • • • • • • • • • • 14.
Atmel AVR XMEGA AU There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0. Only Timer/Counter 0 has the split mode feature that split it into 2 8-bit Timer/Counters with four compare channels each. Some timer/counters have extensions to enable more specialized waveform and frequency generation.
Atmel AVR XMEGA AU “compare channels.” When used for capture operations, the CC channels are referred to as “capture channels.” 14.3 Block Diagram Figure 14-2 on page 170 shows a detailed block diagram of the timer/counter without the extensions. Figure 14-2. Timer/counter block diagram. Base Counter BV PERBUF CTRLA PER CTRLD Clock Select Event Select "count" "clear" "load" "direction" Counter CNT OVF/UNF (INT/DMA Req.) Control Logic ERRIF = =0 TOP BOTTOM "ev" UPDATE (INT Req.
Atmel AVR XMEGA AU A prescaled peripheral clock and events from the event system can be used to control the counter. The event system is also used as a source to the input capture. Combined with the quadrature decoding functionality in the event system (QDEC), the timer/counter can be used for quadrature decoding. 14.4 Clock and Event Sources The timer/counter can be clocked from the peripheral clock (clkPER) or the event system, and Figure 14-3 shows the clock and event selection. Figure 14-3.
Atmel AVR XMEGA AU Figure 14-4. Period and compare double buffering. "write enable" BV UPDATE "data write" EN CCxBUF EN CCx CNT = "match" When the CC channels are used for a capture operation, a similar double buffering mechanism is used, but in this case the buffer valid flag is set on the capture event, as shown in Figure 14-5. For capture, the buffer register and the corresponding CCx register act like a FIFO.
Atmel AVR XMEGA AU Figure 14-6. Normal operation. CNT written MAX "update" CNT TOP BOTTOM DIR As shown in Figure 14-6, it is possible to change the counter value when the counter is running. The write access has higher priority than count, clear, or reload, and will be immediate. The direction of the counter can also be changed during normal operation. Normal operation must be used when using the counter as timer base for the capture channels. 14.6.
Atmel AVR XMEGA AU Figure 14-7. Changing the period without buffering. Counter Wraparound MAX "update" "write" CNT BOTTOM New TOP written to PER that is higher than current CNT New TOP written to PER that is lower than current CNT A counter wraparound can occur in any mode of operation when up-counting without buffering, as shown in Figure 14-8.
Atmel AVR XMEGA AU 14.7 Capture Channel The CC channels can be used as capture channels to capture external events and give them a timestamp. To use capture, the counter must be set for normal operation. Events are used to trigger the capture; i.e., any events from the event system, including pin change from any pin, can trigger a capture operation. The event source select setting selects which event channel will trigger CC channel A.
Atmel AVR XMEGA AU Figure 14-11. Input capture timing. events TOP CNT BOTTOM Capture 0 14.7.2 Capture 1 Capture 2 Capture 3 Frequency Capture Selecting the frequency capture event action makes the enabled capture channel perform an input capture and restart on positive edge events. This enables the timer/counter to measure the period or frequency of a signal directly. The capture result will be the time (T) from the previous timer/counter restart until the event occurred.
Atmel AVR XMEGA AU 14.7.3 Pulse Width Capture Selecting the pulse width measure event action makes the enabled compare channel perform the input capture action on falling edge events and the restart action on rising edge events. The counter will then restart on positive edge events, and the input capture will be performed on the negative edge event. The event source must be an I/O pin, and the sense configuration for the pin must be set to generate an event on both edges.
Atmel AVR XMEGA AU synchronization prevents the occurrence of odd-length, non-symmetrical pulses for glitch-free output. 14.8.1 Waveform Generation The compare channels can be used for waveform generation on the corresponding port pins. To make the waveform visible on the connected port pin, the following requirements must be fulfilled: 1. A waveform generation mode must be selected. 2. Event actions must be disabled. 3. The CC channels used must be enabled.
Atmel AVR XMEGA AU to TOP and then restarts from BOTTOM. The waveform generator (WG) output is set on the compare match between the CNT and CCx registers and cleared at TOP. Figure 14-15. Single-slope pulse width modulation. Period (T) CCx=BOTTOM CCx=TOP "update" "match" MAX TOP CNT CCx BOTTOM WG Output The PER register defines the PWM resolution. The minimum resolution is 2 bits (PER=0x0003), and the maximum resolution is 16 bits (PER=MAX).
Atmel AVR XMEGA AU Figure 14-16. Dual-slope pulse width modulation. Period (T) CCx=BOTTOM CCx=TOP "update" "match" MAX CCx TOP CNT BOTTOM WG Output Using dual-slope PWM results in a lower maximum operation frequency compared to the singleslope PWM operation. The period register (PER) defines the PWM resolution. The minimum resolution is 2 bits (PER=0x0003), and the maximum resolution is 16 bits (PER=MAX).
Atmel AVR XMEGA AU Figure 14-17. Port override for timer/counter 0 and 1. OUT OCx Waveform CCExEN 14.9 INVEN Interrupts and events The timer/counter can generate both interrupts and events. The counter can generate an interrupt on overflow/underflow, and each CC channel has a separate interrupt that is used for compare or capture. In addition, an error interrupt can be generated if any of the CC channels is used for capture and a buffer overflow condition occurs on a capture channel.
Atmel AVR XMEGA AU 14.12 Register Description 14.12.1 CTRLA – Control register A Bit 7 6 5 4 +0x00 – – – – 3 2 1 0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 CLKSEL[3:0] CTRLA • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU • Bit 3 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 2:0 – WGMODE[2:0]: Waveform Generation Mode These bits select the waveform generation mode, and control the counting sequence of the counter, TOP value, UPDATE condition, interrupt/event condition, and type of waveform that is generated according to Table 14-4 on page 183.
Atmel AVR XMEGA AU 14.12.4 CTRLD – Control register D Bit 7 +0x03 6 5 EVACT[2:0] 4 3 2 EVDLY 1 0 EVSEL[3:0] CTRLD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:5 – EVACT[2:0]: Event Action These bits define the event action the timer will perform on an event according to Table 14-5 on page 184. The EVSEL setting will decide which event source or sources have control in this case. Table 14-5. Timer event action selection.
Atmel AVR XMEGA AU Table 14-6. Timer event source selection. EVSEL[3:0] Group Configuration 0000 OFF None 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1nnn 14.12.5 Event Source CHn Event channel n, n={0,...
Atmel AVR XMEGA AU • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 3:2 – ERRINTLVL[1:0]:Timer Error Interrupt Level These bits enable the timer error interrupt and select the interrupt level as described in ”Interrupts and Programmable Multilevel Interrupt Controller” on page 134.
Atmel AVR XMEGA AU • Bit 3:2 – CMD[1:0]: Command These bits can be used for software control of update, restart, and reset of the timer/counter. The command bits are always read as zero. Table 14-8.
Atmel AVR XMEGA AU 14.12.10 INTFLAGS – Interrupt Flag register Bit 7 6 5 4 3 2 1 0 CCDIF CCCIF CCBIF CCAIF – – ERRIF OVFIF Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x0C INTFLAGS • Bit 7:4 – CCxIF: Compare or Capture Channel x Interrupt Flag The compare or capture interrupt flag (CCxIF) is set on a compare match or on an input capture event on the corresponding CC channel.
Atmel AVR XMEGA AU For more details, refer to ”Accessing 16-bit Registers” on page 13. Bit 7 6 5 4 +0x0F 3 2 1 0 TEMP[7:0] TEMP Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 14.12.12 CNTL – Counter register L The CNTH and CNTL register pair represents the 16-bit value, CNT. CNT contains the 16-bit counter value in the timer/counter. CPU and DMA write access has priority over count, clear, or reload of the counter.
Atmel AVR XMEGA AU 14.12.15 PERH – Period register H Bit 7 6 5 4 3 +0x27 2 1 0 PER[15:8] PERH Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 • Bit 7:0 – PER[15:8] These bits hold the MSB of the 16-bit period register. 14.12.16 CCxL – Compare or Capture x register L The CCxH and CCxL register pair represents the 16-bit value, CCx. These 16-bit register pairs have two functions, depending of the mode of operation.
Atmel AVR XMEGA AU • Bit 7:0 – PERBUF[7:0] These bits hold the LSB of the 16-bit period buffer register. 14.12.19 PERBUFH – Timer/Counter Period Buffer H Bit 7 6 5 4 Read/Write R/W R/W R/W R/W Initial Value 1 1 1 1 +0x37 3 2 1 0 R/W R/W R/W R/W 1 1 1 1 PERBUF[15:8] PERBUFH • Bit 7:0 – PERBUF[15:8] These bits hold the MSB of the 16-bit period buffer register. 14.12.
Atmel AVR XMEGA AU 14.
Atmel AVR XMEGA AU 15. TC2 – 16-bit Timer/Counter Type 2 15.1 Features • A system of two eight-bit timer/counters • • • • • • 15.
Atmel AVR XMEGA AU 15.3 Block Diagram Figure 15-1. Block diagram of the 16-bit timer/counter 0 with split mode. Base Counter HPER "count high" "load high" "count low" "load low" Counter HCNT Clock Select CTRLA LPER LCNT HUNF Control Logic (INT/DMA Req.) LUNF (INT/DMA Req.) =0 BOTTOML BOTTOMH =0 Compare (Unit x = {A,B,C,D}) LCMPx = Waveform Generation OCLx Out LCMPx "match" (INT/DMA Req.) Compare (Unit x = {A,B,C,D}) HCMPx = 15.
Atmel AVR XMEGA AU Figure 15-2. Clock selection. Common Prescaler clkPER Event System clkPER / 2{0,...,15} clkPER / {1,2,4,8,64,256,1024} events event channels CLKSEL CNT The peripheral clock (clkPER) is fed into the common prescaler (common for all timer/counters in a device). A selection of prescaler outputs from 1 to 1/1024 is directly available. In addition, the whole range of time prescalings from 1 to 215 is available through the event system.
Atmel AVR XMEGA AU Figure 15-4. Changing the period. MAX "reload" "write" CNT BOTTOM New TOP written to PER that is higher than current CNT 15.6 New TOP written to PER that is lower than current CNT Compare Channel Each compare channel continuously compares the counter value with the CMPx register. If CNT equals CMPx, the comparator signals a match.
Atmel AVR XMEGA AU The PER register defines the PWM resolution. The minimum resolution is two bits (PER=0x0003), and the maximum resolution is eight bits (PER=MAX).
Atmel AVR XMEGA AU 15.8 DMA Support Timer/counter underflow and compare interrupt flags can trigger a DMA transaction. The acknowledge condition that clears the flag/request is listed in Table 15-1 on page 198. Table 15-1. 15.9 DMA request sources.
Atmel AVR XMEGA AU 15.10 Register Description 15.10.1 CTRLA – Control register A Bit 7 6 5 4 +0x00 – – – – 3 2 1 0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 CLKSEL[3:0] CTRLA • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU 15.10.3 CTRLC – Control register C Bit 7 6 5 4 3 2 1 0 HCMPD HCMPC HCMPB HCMPA LCMPD LCMPC LCMPB LCMPA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x02 CTRLC • Bit 7:0 – HCMPx/LCMPx: High/Low Compare x Output Value These bits allow direct access to the waveform generator's output compare value when the timer/counter is OFF. This is used to set or clear the WG output value when the timer/counter is not running. 15.10.
Atmel AVR XMEGA AU • Bit 3:2 – HUNFINTLVL[1:0]: High-byte Timer Underflow Interrupt Level These bits enable the high-byte timer underflow interrupt and select the interrupt level, as described in ”Interrupts and Programmable Multilevel Interrupt Controller” on page 134. The enabled interrupt will be triggered when HUNFIF in the INTFLAGS register is set.
Atmel AVR XMEGA AU • Bit 1:0 – CMDEN[1:0]: Command Enable These bits are used to indicate for which timer/counter the command (CMD) is valid. Table 15-5. 15.10.8 Command selections.
Atmel AVR XMEGA AU 15.10.10 HCNT – High-byte Count register Bit 7 6 5 4 3 +0x21 2 1 0 HCNT[7:0] HCNT Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – HCNT[7:0] HCNT contains the eight-bit counter value for the high-byte timer/counter. The CPU and DMA write accesses have priority over count, clear, or reload of the counter. 15.10.
Atmel AVR XMEGA AU 15.10.14 HCMPx – High-byte Compare register x Bit 7 6 5 4 3 2 1 0 HCMPx[7:0] HCMPx Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – HCMPx[7:0], x=[A, B, C, D] HCMPx contains the eight-bit compare value for the high-byte timer/counter. These registers are all continuously compared to the counter value. Normally the outputs from the comparators are then used for generating waveforms.
Atmel AVR XMEGA AU 15.
Atmel AVR XMEGA AU 16. AWeX – Advanced Waveform Extension 16.
Atmel AVR XMEGA AU output pairs go through a dead-time insertion (DTI) unit that generates the non-inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting. Refer to ”I/O Ports” on page 143 for more details. The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to.
Atmel AVR XMEGA AU Figure 16-2. Timer/counter extensions and port override logic.
Atmel AVR XMEGA AU The DTI unit consists of four equal dead-time generators, one for each compare channel in timer/counter 0. Figure 16-3 on page 209 shows the block diagram of one DTI generator. The four channels have a common register that controls the dead time. The high side and low side have independent dead-time setting, and the dead-time registers are double buffered. Figure 16-3. Dead-time generator block diagram.
Atmel AVR XMEGA AU cations. A block diagram of the pattern generator is shown in ”Pattern generator block diagram.” on page 210. For each port pin where the corresponding OOE bit is set, the multiplexer will output the waveform from CCA. Figure 16-5. Pattern generator block diagram.
Atmel AVR XMEGA AU 16.6.2 Fault Restore Modes How the AWeX and timer/counter return from the fault state to normal operation after a fault, when the fault condition is no longer active, can be selected from one of two different modes: • In latched mode, the waveform output will remain in the fault state until the fault condition is no longer active and the fault detect flag has been cleared by software.
Atmel AVR XMEGA AU 16.7 16.7.1 Register Description CTRL – Control register Bit 7 6 5 4 3 2 1 0 +0x00 – – PGM CWCM DTICCDEN DTICCCEN DTICCBEN DTICCAEN Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 CTRL • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU • Bit 7:5 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 4 – FDDBD: Fault Detection on Debug Break Detection By default, when this bit is cleared and fault protection is enabled, and OCD break request is treated as a fault. When this bit is set, an OCD break request will not trigger a fault condition. • Bit 3 – Reserved This bit is unused and reserved for future use.
Atmel AVR XMEGA AU • Bit 2 – FDF: Fault Detect Flag This flag is set when a fault detect condition is detected; i.e., when an event is detected on one of the event channels enabled by FDEVMASK. This flag is cleared by writing a one to its bit location. • Bit 1 – DTHSBUFV: Dead-time High Side Buffer Valid If this bit is set, the corresponding DT buffer is written and contains valid data that will be copied into the DTLS register on the next UPDATE condition. If this bit is zero, no action will be taken.
Atmel AVR XMEGA AU • Bit 7:0 – DTLS: Dead-time Low Side This register holds the number of peripheral clock cycles for the dead-time low side. 16.7.8 DTHS – Dead-time High Side register Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x09 DTHS[7:0] DTHS • Bit 7:0 – DTHS: Dead-time High Side This register holds the number of peripheral clock cycles for the dead-time high side. 16.7.
Atmel AVR XMEGA AU • Bit 7:0 – OUTOVEN[7:0]: Output Override Enable These bits enable override of the corresponding port output register (i.e., one-to-one bit relation to pin position). The port direction is not overridden. 16.
Atmel AVR XMEGA AU 17. Hi-Res – High-Resolution Extension 17.1 Features • Increases waveform generator resolution up to 8x (3 bits) • Supports frequency, single-slope PWM, and dual-slope PWM generation • Supports the AWeX when this is used for the same timer/counter 17.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight.
Atmel AVR XMEGA AU The hi-res extension will not output any pulse shorter than one peripheral clock cycle; i.e., a compare value lower than four will have no visible output. 17.3 Register Description 17.3.1 CTRLA – Control register A Bit 7 6 5 4 3 2 +0x00 – – – – – HRPLUS 1 0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 HREN[1:0] CTRLA • Bit 7:3 – Reserved These bits are unused and reserved for future use.
Atmel AVR XMEGA AU 18. RTC – Real-Time Counter 18.1 Features • 16-bit resolution • Selectable clock source • • • • • 18.2 – 32.768kHz external crystal – External clock – 32.
Atmel AVR XMEGA AU 18.2.1 Clock Domains The RTC is asynchronous, operating from a different clock source independently of the main system clock and its derivative clocks, such as the peripheral clock. For control and count register updates, it will take a number of RTC clock and/or peripheral clock cycles before an updated register value is available in a register or until a configuration change has effect on the RTC. This synchronization time is described for each register.
Atmel AVR XMEGA AU 18.3 18.3.1 Register Descriptions CTRL – Control register Bit 7 6 5 4 3 2 1 0 +0x00 – – – – – Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PRESCALER[2:0] CTRL • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU 18.3.2 STATUS – Status register Bit 7 6 5 4 3 2 1 0 +0x01 – – – – – – – SYNCBUSY Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 STATUS • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU 18.3.4 INTFLAGS – Interrupt Flag register Bit 7 6 5 4 3 2 1 0 +0x03 – – – – – – COMPIF OVFIF Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 INTFLAGS • Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU • Bit 7:0 – CNT[7:0]: Counter Value Low These bits hold the LSB of the 16-bit real-time counter value. 18.3.7 CNTH – Counter Register High Bit 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x09 CNT[15:8] CNTH • Bit 7:0 – CNT[15:8]: Counter Value High These bits hold the MSB of the 16-bit real-time counter value. 18.3.8 PERL – Period Register Low The PERH and PERL register pair represents the 16-bit value, PER.
Atmel AVR XMEGA AU 18.3.10 COMPL – Compare Register Low The COMPH and COMPL register pair represent the 16-bit value, COMP. COMP is constantly compared with the counter value (CNT). A compare match will set COMPIF in the INTFLAGS register. Reading and writing 16-bit values requires special attention. Refer ”Accessing 16-bit Registers” on page 13 for details.
Atmel AVR XMEGA AU 18.4 Register Summary Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 +0x00 CTRL – – – – – +0x01 STATUS – – – – – +0x02 INTCTRL – – – – COMPINTLVL[1:0] +0x03 INTFLAGS – – – – – +0x04 TEMP TEMP[7:0] 223 +0x08 CNTL CNT[7:0] 224 +0x09 CNTH CNT[15:8] 223 +0x0A PERL PER[7:0] 224 +0x0B PERH PER[15:8] 224 +0x0C COMPL COMP[7:0] 225 +0x0D COMPH COMP[15:8] 225 18.
Atmel AVR XMEGA AU 19. RTC32 – 32-bit Real-Time Counter 19.1 Features • 32-bit resolution • 32.768kHz external crystal clock source with selectable prescaling • • • • 19.2 – 1.024kHz – 1Hz One compare register One period register Clear counter on period overflow Optional interrupt/ event on overflow and compare match Overview The 32-bit real-time counter (RTC32) is a 32-bit counter that typically runs continuously, including in low-power sleep modes, to keep track of time.
Atmel AVR XMEGA AU The Peripheral clock must be more than eight times faster than the RTC32 clock (1.024kHz or 1Hz) when any of the Control or the Count register are accessed (read or written), more than 12 times faster when the Count register is written. 19.2.3 Power Domains For devices where the RTC32 is located in the VBAT power domain, the battery backup feature enables the RTC32 to also function with no main VCC available.
Atmel AVR XMEGA AU 19.3 19.3.1 Register Descriptions CTRL – Control register Bit 7 6 5 4 3 2 1 0 +0x00 – – – – – – – ENABLE Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 CTRL • Bit 7:1 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 0 – ENABLE: Enable Setting this bit enables the RTC32.
Atmel AVR XMEGA AU 19.3.3 INTCTRL – Interrupt Control register Bit 7 6 5 4 3 2 1 0 +0x02 – – – – COMPINTLVL[1:0] Read/Write R R R R R/W R/W R/W R/W Reset Value 0 0 0 0 0 0 0 0 OCINTLVL[1:0] INTCTRL • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU Synchronization of a new CNT value to the RTC32 domain is triggered by writing CNT3. The synchronization time is up to 12 peripheral clock cycles from updating the register until this has an effect in the RTC32 domain. Write operations to the CNT register will be blocked if the SYNCBUSY flag is set. The synchronization of the CNT register value from the RTC32 domain to the system clock domain can be done by writing one to the SYNCCNT bit in the SYNCCTRL register.
Atmel AVR XMEGA AU After writing a byte in the PER register, the write (HW/SW) condition for setting OVFIF and the overflow wake-up condition are disabled for the following two RTC32 clock cycles. Bit 7 6 5 4 3 +0x08 19.3.
Atmel AVR XMEGA AU Bit 7 6 5 4 +0x0C 19.3.14 1 0 COMP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 COMP1 – Compare register 1 +0x0D COMP[15:8] COMP1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 COMP2 – Compare register 2 Bit +0x0E 19.3.16 2 COMP[7:0] Bit 19.3.
Atmel AVR XMEGA AU 19.
Atmel AVR XMEGA AU 20. USB – Universal Serial Bus Interface 20.1 Features • USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface • Integrated on-chip USB transceiver, no external components needed • 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints • • • • • • • • • • • • 20.
Atmel AVR XMEGA AU To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer while the USB module writes/reads the others, and vice versa. This gives double buffered communication. Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention.
Atmel AVR XMEGA AU 20.3 Operation This section gives an overview of the USB module operation during normal transactions. For general details on USB and the USB protocol, please refer to http://www.usb.org and the USB specification documents. 20.3.
Atmel AVR XMEGA AU Finally, the setup transaction complete flag (SETUP), data buffer 0 not acknowledge flag (NACK0), and data toggle flag (TOGGLE) are set, while the remaining flags in the endpoint status register (STATUS) are cleared for the addressed input and output endpoints. The setup transaction complete interrupt flag (SETUPIF) in INTFLAGSBCLR/SET is set. The STALL flag in the endpoint CTRL register is cleared for the addressed input and output endpoints.
Atmel AVR XMEGA AU The incoming data are written to the data buffer pointed to by DATAPTR. If a bit-stuff error is detected in the incoming data, the USB module returns to idle and waits for the next token packet. If the number of received data bytes exceeds the maximum data payload specified by SIZE, the remaining received data bytes are discarded. The packet will still be checked for bitstuff and CRC errors.
Atmel AVR XMEGA AU BUSNACK0 and TRNCOMPL0 are set and TOGGLE is toggled. TRNIF is set and the endpoint's configuration table address is written to the FIFO if the transcation complete FIFO mode is enabled. When an IN token is detected and the device address of the token packet does not match that of the endpoint, the packet is discarded and the USB module returns to idle and waits for the next token packet. Figure 20-5. IN transaction.
Atmel AVR XMEGA AU Figure 20-6. SRAM memory mapping. EP_ADDRH_MAX FIFO (MAXEP+1) x 4 Bytes Active when FIFOEN==1 EPPTR ENDPOINT DESCRIPTORS TABLE EPPTR + (MAXEP+1)*16 SRAM ADDRESS 20.
Atmel AVR XMEGA AU Figure 20-7. Clock generation configuration. USBSRC 48MHz full speed USB module 6MHz for low speed USB clock prescaler PLL 48MHz Internal Oscillator USBPSDIV 20.6 Ping-pong Operation When an endpoint is configured for ping-pong operation, it uses the input and output data buffers to create a single, double-buffered endpoint that can be set to input or output direction.
Atmel AVR XMEGA AU Figure 20-8. Ping-pong operation overview. Endpoint single bank Without Ping-Pong t Endpoint Double bank With Ping-Pong t USB data packet Bank0 Bank1 Available time for data processing by CPU to avoid NACK 20.7 Multipacket Transfers Multipacket transfer enables a data payload exceeding the maximum data payload size of an endpoint to be transferred as multiple packets without any software intervention.
Atmel AVR XMEGA AU When an IN token is received, the endpoint’s CNT and AUXDATA are fetched. If CNT minus AUXDATA is less than the endpoint SIZE, endpoint CNT minus endpoint AUXDATA number bytes are transmitted; otherwise, SIZE number of bytes are transmitted. If endpoint CNT is a multiple of SIZE and auto zero length packet (AZLP) is enabled, the last packet sent will be zero length. If a maximum payload size packet was sent (i.e., not the last transaction), AUXDATA is incremented by SIZE.
Atmel AVR XMEGA AU Figure 20-10. Transfer complete FIFO. INTERNAL SRAM EPPTR– 4x( MAXEP+1) TC_ EP_ ADDRH_ MAX USB_ TC_ FIFO TC_ EP_ ADDRH_2 TC_ EP_ ADDRH_2 TC_EP_ ADDRL_1 TC_ EP_ ADDRH_1 FIFOWP TC_EP_ ADDRL_0 FIFORP TC_EP_ ADDRH_0 EPPTR ENDPOINT DESCRIPTOR TABLE SRAM ADDRESS To manage the FIFO, a five-bit write pointer (FIFOWP) and five-bit read pointer (FIFORP) are used by the USB module and application software, respectively.
Atmel AVR XMEGA AU Figure 20-12 on page 246 summarizes the interrupts and event sources for the USB module, and shows how they are enabled. Figure 20-12. Interrupts and events scheme summary. SOFIF SUSPENDIF SOFIE RESUMEIF RSTIF BSEVIE Busevent Interrupt request CRCIF UNFIF OVFIF BUSSERRIE STALLIF STALLIE SETUPIF SETUPIE Transaction Complete Interrupt request TRNIF TRNIE 20.10.1 Transaction Complete Interrupt The transaction complete interrupt is generated per endpoint.
Atmel AVR XMEGA AU 20.10.2 Bus Event Interrupt The bus event (BUSEVENT) interrupt is used for all interrupts that signal various types of USB line events or error conditions. These interrupts are related to the USB lines, and are generated for the USB module and per endpoint. The following eight interrupts use the interrupt vector: Table 20-2. 20.10.3 Bus event interrupt source.
Atmel AVR XMEGA AU 20.13 Register Description – USB 20.13.1 CTRLA – Control register A Bit 7 6 5 4 ENABLE SPEED FIFOEN STFRNUM Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x00 3 2 1 0 MAXEP[3:0] CTRLA • Bit 7 – ENABLE: USB Enable Setting this bit enables the USB interface. Clearing this bit disables the USB interface and immediately aborts any ongoing transactions.
Atmel AVR XMEGA AU • Bit 4 – PULLRST: Pull during Reset Setting this bit enables the pull-up on the USB lines to also be held when the device enters reset. The bit will be cleared on a power-on reset. • Bit 3 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written.
Atmel AVR XMEGA AU 20.13.4 ADDR – Address register Bit 7 6 5 4 3 2 1 0 +0x03 – Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADDR[6:0] ADDR • Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written. • Bit 6:0 – ADDR[6:0]: Device Address These bits contain the USB address the device will respond to. 20.13.
Atmel AVR XMEGA AU 20.13.7 EPPTRL – Endpoint Configuration Table Pointer Low Byte The EPPTRL and EPPTRH registers represent the 16-bit value, EPPTR, that contains the address to the endpoint configuration table. The pointer to the endpoint configuration table must be aligned to a 16-bit word; i.e., EPPTR[0] must be zero. Only the number of bits required to address the available internal SRAM memory is implemented for each device. Unused bits will always be read as zero.
Atmel AVR XMEGA AU • Bit 5 – BUSERRIE: Bus Error Interrupt Enable Setting this bit will enable the interrupt for the following three bus error events: 1. Isochronous CRC Error: An interrupt will be generated for the conditions that set the CRC interrupt flag (CRCIF) in the INTFLAGSACLR/SET register during isochronous transfers. 2. Underflow: An interrupt will be generated for the conditions that set the undeflow interrupt flag (UNFIF) in the INTFLAGSACLR/SET register. 3.
Atmel AVR XMEGA AU FLAGSACLR. Both memory locations will provide the same result when read, and writing zero to any bit location has no effect. Bit +0x0A/ +0x0B 7 6 5 4 3 2 1 0 SOFIF SUSPENDIF RESUMEIF RESETIF CRCIF UNFIF OVFIF STALLIF Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – SOFIF: Start Of Frame Interrupt Flag This flag is set when a start of frame packet has been received.
Atmel AVR XMEGA AU • Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 1 – TRNIF: Transaction Complete Interrupt Flag This flag is when there is a pending packet interrupt in the FIFO. • Bit 0 – SETUPIF: SETUP Transaction Complete Interrupt Flag This flag is set when a SETUP transaction has completed successfully. 20.13.
Atmel AVR XMEGA AU 20.14 Register Description – USB Endpoint Each of the 16 endpoint addresses have one input and one output endpoint. Each endpoint has eight bytes of configuration/status data located in internal SRAM. The address to the first configuration byte is (EPPTR[15:0] + 16 × endpoint address) for output endpoints and (EPPTR[15:0] + 16 × endpoint address + 8) for input endpoints.
Atmel AVR XMEGA AU • Bit 3 – BANK: Bank Select Flag When ping-pong mode is enabled, this bit indicates which bank will be used for the next transaction. BANK is toggled each time a transaction has completed successfully. This bit is not sed when ping-pong is disabled. This flag is cleared by writing a one to its bit location.
Atmel AVR XMEGA AU interrupts or software intervention. See ”Multipacket Transfers” on page 243 for details on multipacket transfers. • Bit 4 – PINGPONG: Ping-pong Enable Setting this bit enables ping-pong operation. Ping-pong operation enables both endpoints (IN and OUT) with same address to be used in the same direction to allow double buffering and maximize throughput. The endpoint in the opposite direction must be disabled when ping-pong operation is enabled.
Atmel AVR XMEGA AU Bit 7 6 5 4 +0x02 3 2 1 0 CNT[7:0] CNTL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X 1 0 • Bit 7:0 – CNT[7:0]: Endpoint Byte Counter This byte contains the eight lsbs of the USB endpoint counter (CNT). 20.14.
Atmel AVR XMEGA AU • Bit 15:0 - DPTR[15:8]: Endpoint Data Pointer High This byte contains the eight msbs of the endpoint data pointer (DATAPTR). 20.14.7 AUXDATAL – Auxiliary Data Low The AUXDATAL and AUXDATAH registers represent the 16-bit value, AUXDATA, that is used for multipacket transfers. For IN endpoints, AUXDATA holds the total number of bytes sent. AUXDATA should be written to zero when setting up a new transfer. For OUT endpoints, AUXDATA holds the total data size for the complete transfer.
Atmel AVR XMEGA AU 20.15 Register Description – Frame 20.15.1 FRAMENUML – Frame Number Low The FRAMENUML and FRAMENUMH registers represent the 11-bit value, FRAMENUM, that holds the frame number from the most recently received start of frame packet. Bit 7 6 5 Read/Write R R R R Initial Value 0 0 0 0 +0x00 4 3 2 1 0 R R R R 0 0 0 0 1 0 FRAMENUM[7:0] FRAMENUML • Bit 7:0 – FRAMENUM[7:0]: Frame Number This byte contains the eight lsb sof the frame number (FRAMENUM). 20.15.
Atmel AVR XMEGA AU 20.
Atmel AVR XMEGA AU 21. TWI – Two-Wire Interface 21.1 Features • Bidirectional, two-wire communication interface • • • • • • • • • 21.
Atmel AVR XMEGA AU 21.3 General TWI Bus Concepts The TWI provides a simple, bidirectional, two-wire communication bus consisting of a serial clock line (SCL) and a serial data line (SDA). The two lines are open-collector lines (wired-AND), and pull-up resistors (Rp) are the only external components needed to drive the bus.
Atmel AVR XMEGA AU Figure 21-2. Basic TWI transaction diagram topology for a 7-bit address bus . SDA SCL 6 ... 0 S ADDRESS S ADDRESS 7 ... 0 R/W R/W ACK A DATA DATA 7 ...
Atmel AVR XMEGA AU 21.3.3 Bit Transfer As illustrated by Figure 21-4, a bit transferred on the SDA line must be stable for the entire high period of the SCL line. Consequently the SDA value can only be changed during the low period of the clock. This is ensured in hardware by the TWI module. Figure 21-4. Data validity. SDA SCL DATA Valid Change Allowed Combining bit transfers results in the formation of address and data packets.
Atmel AVR XMEGA AU Figure 21-5. Master write transaction. Transaction Data Packet Address Packet S ADDRESS W A DATA A DATA A/A P N data packets Assuming the slave acknowledges the address, the master can start transmitting data (DATA) and the slave will ACK or NACK (A/A) each byte. If no data packets are to be transmitted, the master terminates the transaction by issuing a STOP condition (P) directly after the address packet.
Atmel AVR XMEGA AU Three types of clock stretching can be defined, as shown in Figure 21-8. Figure 21-8. Clock stretching(1). bit 7 SDA bit 6 bit 0 ACK/NACK SCL S Wakeup clock stretching Note: Periodic clock stretching Random clock stretching 1. Clock stretching is not supported by all I2C slaves and masters. If a slave device is in sleep mode and a START condition is detected, the clock stretching normally works during the wake-up period.
Atmel AVR XMEGA AU Figure 21-9 shows an example where two TWI masters are contending for bus ownership. Both devices are able to issue a START condition, but DEVICE1 loses arbitration when attempting to transmit a high level (bit 5) while DEVICE2 is transmitting a low level. Arbitration between a repeated START condition and a data bit, a STOP condition and a data bit, or a repeated START condition and a STOP condition are not allowed and will require special handling by software. 21.3.
Atmel AVR XMEGA AU Figure 21-11. Bus state, state diagram. RESET UNKNOWN (0b00) P + Timeout S Sr IDLE BUSY P + Timeout (0b01) (0b11) Command P Arbitration Lost Write ADDRESS (S) OWNER (0b10) Write ADDRESS(Sr) After a system reset and/or TWI master enable, the bus state is unknown. The bus state machine can be forced to enter idle by writing to the bus state bits accordingly. If no state is set by application software, the bus state will become idle when the first STOP condition is detected.
Atmel AVR XMEGA AU When an interrupt flag is set, the SCL line is forced low. This will give the master time to respond or handle any data, and will in most cases require software interaction. Figure 21-12 shows the TWI master operation. The diamond shaped symbols (SW) indicate where software interaction is required. Clearing the interrupt flags releases the SCL line. Figure 21-12. TWI master operation.
Atmel AVR XMEGA AU 21.5.1.2 Case M2: Address packet transmit complete - Address not acknowledged by slave If no slave device responds to the address, the master write interrupt flag and the master received acknowledge flag are set. The clock hold is active at this point, preventing further activity on the bus. 21.5.1.
Atmel AVR XMEGA AU Figure 21-13. TWI slave operation. SLAVE ADDRESS INTERRUPT S1 S3 S2 S A ADDRESS R SW P S2 Sr S3 DATA SW S1 P S2 Sr S3 A/A Driver software The master provides data on the bus Slave provides data on the bus Sn S1 A A SW SLAVE DATA INTERRUPT W SW Interrupt on STOP Condition Enabled SW Collision (SMBus) SW A/A Release Hold DATA SW A/A S1 Diagram connections The number of interrupts generated is kept to a minimum by automatic handling of most conditions.
Atmel AVR XMEGA AU received. Data, repeated START, or STOP can be received after this. If NACK is sent, the slave will wait for a new START condition and address match. 21.6.1.3 Case S3: Collision If the slave is not able to send a high level or NACK, the collision flag is set, and it will disable the data and acknowledge output from the slave logic. The clock hold is released. A START or repeated START condition will be accepted. 21.6.1.4 Case S4: STOP condition received.
Atmel AVR XMEGA AU 21.8 21.8.1 Register Description – TWI CTRL – Common Control Register Bit 7 6 5 4 3 2 1 0 +0x00 – – – – – SDAHOLD[1:0] Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EDIEN CTRL • Bit 7:3 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 2:1 – SDAHOLD[1:0]: SDA Hold Time Enable.
Atmel AVR XMEGA AU 21.9 21.9.1 Register Description – TWI Master CTRLA – Control register A Bit 7 +0x00 6 INTLVL[1:0] 5 4 3 2 1 0 RIEN WIEN ENABLE – – – Read/Write R/W R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 0 0 0 CTRLA • Bit 7:6 – INTLVL[1:0]: Interrupt Level These bits select the interrupt level for the TWI master interrupt, as described in ”Interrupts and Programmable Multilevel Interrupt Controller” on page 134.
Atmel AVR XMEGA AU Table 21-3. TWI master inactive bus timeout settings. TIMEOUT[1:0] Group Configuration Description 00 DISABLED 01 50US 50µs, normally used for SMBus at 100kHz 10 100US 100µs 11 200US 200µs Disabled, normally used for I2C • Bit 1 – QCEN: Quick Command Enable When quick command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges the address (read or write interrupt).
Atmel AVR XMEGA AU STOP condition. The ACKACT bit and the CMD bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered. Table 21-5. CMD bits description.
Atmel AVR XMEGA AU • Bit 5 – CLKHOLD: Clock Hold This flag is set when the master is holding the SCL line low. This is a status flag and a read-only flag that is set when RIF or WIF is set. Clearing the interrupt flags and releasing the SCL line will indirectly clear this flag. The flag is also cleared automatically for the same conditions as RIF. • Bit 4 – RXACK: Received Acknowledge This flag contains the most recently received acknowledge bit from the slave. This is a read-only flag.
Atmel AVR XMEGA AU The baud rate (BAUD) register defines the relation between the system clock and the TWI bus clock (SCL) frequency. The frequency relation can be expressed by using the following equation: f sys f TWI = ---------------------------------------- [Hz] 2(5 + ( BAUD )) [1] The BAUD register must be set to a value that results in a TWI bus clock frequency (fTWI) equal or less than 100kHz or 400kHz, depending on which standard the application should comply with.
Atmel AVR XMEGA AU register can only be accessed when the SCL line is held low by the master; i.e., when CLKHOLD is set. In master write mode, writing the DATA register will trigger a data byte transfer followed by the master receiving the acknowledge bit from the slave. WIF and CLKHOLD are set. In master read mode, RIF and CLKHOLD are set when one byte is received in the DATA register. If smart mode is enabled, reading the DATA register will trigger the bus operation as set by the ACKACT bit.
Atmel AVR XMEGA AU • Bit 0 – SMEN: Smart Mode Enable This bit enables smart mode. When Smart mode is enabled, the acknowledge action, as set by the ACKACT bit in the CTRLB register, is sent immediately after reading the DATA register. 21.10.2 CTRLB – Control register B Bit 7 6 5 4 3 2 1 0 +0x01 – – – – – ACKACT Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 CMD[1:0] CTRLB • Bit 7:3 – Reserved These bits are unused and reserved for future use.
Atmel AVR XMEGA AU Table 21-8. TWI slave command.
Atmel AVR XMEGA AU • Bit 4 – RXACK: Received Acknowledge This flag contains the most recently received acknowledge bit from the master. This is a readonly flag. When read as zero, the most recent acknowledge bit from the maser was ACK, and when read as one, the most recent acknowledge bit was NACK. • Bit 3 – COLL: Collision This flag is set when a slave has not been able to transfer a high data bit or a NACK bit.
Atmel AVR XMEGA AU When using 10-bit addressing, the address match logic only supports hardware address recognition of the first byte of a 10-bit address. By setting ADDR[7:1] = 0b11110nn, ”nn” represents bits 9 and 8 of the slave address. The next byte received is bits 7 to 0 in the 10-bit address, and this must be handled by software. When the address match logic detects that a valid address byte is received, APIF is set and the DIR flag is updated.
Atmel AVR XMEGA AU mask bit is one, the address match between the incoming address bit and the corresponding bit in ADDR is ignored; i.e., masked bits will always match. If ADDREN is set to one, ADDRMASK can be loaded with a second slave address in addition to the ADDR register. In this mode, the slave will match on two unique addresses, one in ADDR and the other in ADDRMASK. • Bit 0 – ADDREN: Address Enable By default, this bit is zero, and the ADDRMASK bits acts as an address mask to the ADDR register.
Atmel AVR XMEGA AU 21.11 Register Summary - TWI Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 – – – – – +0x00 CTRL +0x01 MASTER Offset address for TWI Master +0x08 SLAVE Offset address for TWI Slave Bit 2 Bit 1 SDAHOLD Bit 0 Page EDIEN 274 21.
Atmel AVR XMEGA AU 22. SPI – Serial Peripheral Interface 22.1 Features • • • • • • • • 22.2 Full-duplex, three-wire synchronous data transfer Master or slave operation Lsb first or msb first data transfer Eight programmable bit rates Interrupt flag at the end of transmission Write collision flag to indicate data collision Wake up from idle sleep mode Double speed master mode Overview The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins.
Atmel AVR XMEGA AU When the SPI module is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 22-1. The pins with user-defined direction must be configured from software to have the correct direction according to the application. Table 22-1. 22.3 SPI pin override and directions.
Atmel AVR XMEGA AU 22.5 Data Modes There are four combinations of SCK phase and polarity with respect to serial data. The SPI data transfer formats are shown in Figure 22-2. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle. Figure 22-2. SPI transfer modes.
Atmel AVR XMEGA AU 22.7 22.7.1 Register Description CTRL – Control register Bit 7 6 5 4 CLK2X ENABLE DORD MASTER Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 +0x00 3 2 MODE[1:0] 1 0 PRESCALER[1:0] CTRL • Bit 7 – CLK2X: Clock Double When this bit is set, the SPI speed (SCK frequency) will be doubled in master mode (see Table 22-3 on page 291). • Bit 6 – ENABLE: Enable Setting this bit enables the SPI module.
Atmel AVR XMEGA AU Table 22-3. 22.7.2 Relationship between SCK and the peripheral clock (ClkPER) frequency.
Atmel AVR XMEGA AU • Bit 6 – WRCOL: Write Collision Flag The WRCOL flag is set if the DATA register is written during a data transfer. This flag is cleared by first reading the STATUS register when WRCOL is set, and then accessing the DATA register. • Bit 5:0 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. 22.7.
Atmel AVR XMEGA AU 23. USART 23.1 Features • Full-duplex operation • Asynchronous or synchronous operation • • • • • • • 23.
Atmel AVR XMEGA AU Figure 23-1. USART block diagram.
Atmel AVR XMEGA AU 23.3 Clock Generation The clock used for baud rate generation and for shifting and sampling data bits is generated internally by the fractional baud rate generator or externally from the transfer clock (XCK) pin. Five modes of clock generation are supported: normal and double-speed asynchronous mode, master and slave synchronous mode, and master SPI mode. Figure 23-2. Clock generation logic, block diagram.
Atmel AVR XMEGA AU Table 23-1. Equations for calculating baud rate register settings.
Atmel AVR XMEGA AU 23.3.3 Double Speed Operation Double speed operation allows for higher baud rates under asynchronous operation with lower peripheral clock frequencies. When this is enabled, the baud rate for a given asynchronous baud rate setting shown in Table 23-1 on page 296 will be doubled. In this mode, the receiver will use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery.
Atmel AVR XMEGA AU Table 23-2. INVEN and UCPHA functionality. SPI Mode INVEN UCPHA Leading Edge Trailing Edge 0 0 0 Rising, sample Falling, setup 1 0 1 Rising, setup Falling, sample 2 1 0 Falling, sample Rising, setup 3 1 1 Falling, setup Rising, sample The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock cycle. Figure 23-4. UCPHA and INVEN data transfer timing diagrams. UCPHA=0 UCPHA=1 UCPOL=0 23.
Atmel AVR XMEGA AU Figure 23-5. Frame formats. FRAME (IDLE) St (n) P Sp IDLE St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) Start bit, always low. Data bits (0 to 8). Parity bit, may be odd or even. Stop bit, always high. No transfers on the communication line (RxD or TxD). The IDLE state is always high. 23.4.1 Parity Bit Calculation Even or odd parity can be selected for error checking.
Atmel AVR XMEGA AU 23.6.1 Sending Frames A data transmission is initiated by loading the transmit buffer (DATA) with the data to be sent. The data in the transmit buffer are moved to the shift register when the shift register is empty and ready to send a new frame. The shift register is loaded if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. When the shift register is loaded with data, it will transfer one complete frame.
Atmel AVR XMEGA AU 23.7.3 Parity Checker When enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit of the corresponding frame. If a parity error is detected, the parity error flag is set. 23.7.4 Disabling the Receiver A disabling of the receiver will be immediate. The receiver buffer will be flushed, and data from ongoing receptions will be lost. 23.7.
Atmel AVR XMEGA AU 23.8.2 Asynchronous Data Recovery The data recovery unit uses sixteen samples in normal mode and eight samples in double speed mode for each bit. Figure 23-7 on page 302 shows the sampling process of data and parity bits. Figure 23-7. Sampling of data and parity bits.
Atmel AVR XMEGA AU ( D + 1 )S R slow = ------------------------------------------S – 1 + D ⋅ S + SF D S SF SM Rslow Rfast ( D + 2 )S R fast = ----------------------------------( D + 1 )S + S M Sum of character size and parity size (D = 5 to 10 bits). Samples per bit. S = 16 for normal speed mode and S = 8 for double speed mode. First sample number used for majority voting. SF = 8 for normal speed mode and SF = 4 for double speed mode. Middle sample number used for majority voting.
Atmel AVR XMEGA AU 23.9 Fractional Baud Rate Generation Fractional baud rate generation is possible for asynchronous operation due to the relatively high number of clock cycles for each frame. Each bit is sampled sixteen times, but only the three middle samples are of importance. The total number of samples for one frame is also relatively high.
Atmel AVR XMEGA AU Figure 23-9. Fractional baud rate example. BSEL=0 BSCALE=0 fBAUD=fPER/8 clkBAUD8 BSEL=3 BSCALE=-6 fBAUD=fPER/8.375 clkBAUD8 Extra clock cycle added BSEL=3 BSCALE=-4 fBAUD=fPER/9.
Atmel AVR XMEGA AU Table 23-5. USART Baud rate. Baud rate (bps) fOSC = 32.0000MHz CLK2X = 0 CLK2X = 1 BSEL BSCALE Error [%] BSEL BSCALE Error [%] 2400 12 6 0.2 12 7 0.2 4800 12 5 0.2 12 6 0.2 9600 12 4 0.2 12 5 0.2 34 2 0.8 34 3 0.8 138 0 -0.1 138 1 -0.1 12 3 0.2 12 4 0.2 34 1 -0.8 34 2 -0.8 137 -1 -0.1 138 0 -0.1 12 2 0.2 12 3 0.2 34 0 -0.8 34 1 -0.8 135 -2 -0.1 137 -1 -0.1 12 1 0.2 12 2 0.2 33 -1 -0.8 34 0 -0.
Atmel AVR XMEGA AU 23.10 USART in Master SPI Mode Using the USART in master SPI mode requires the transmitter to be enabled. The receiver can optionally be enabled to serve as the serial input. The XCK pin will be used as the transfer clock. As for the USART, a data transfer is initiated by writing to the DATA register. This is the case for both sending and receiving data, since the transmitter controls the transfer clock.
Atmel AVR XMEGA AU If the receiver is set up to receive frames that contain five to eight data bits, the first stop bit is used to indicate the frame type. If the receiver is set up for frames with nine data bits, the ninth bit is used. When the frame type bit is one, the frame contains an address. When the frame type bit is zero, the frame is a data frame.
Atmel AVR XMEGA AU 23.15 Register Description 23.15.1 DATA – Data register Bit 7 6 5 4 3 2 1 0 RXB[[7:0] +0x00 TXB[[7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART transmit data buffer register (TXB) and USART receive data buffer register (RXB) share the same I/O address and is referred to as USART data register (DATA). The TXB register is the destination for data written to the DATA register location.
Atmel AVR XMEGA AU • Bit 5 – DREIF: Data Register Empty Flag This flag indicates whether the transmit buffer (DATA) is ready to receive new data. The flag is one when the transmit buffer is empty and zero when the transmit buffer contains data to be transmitted that has not yet been moved into the shift register. DREIF is set after a reset to indicate that the transmitter is ready. Always write this bit to zero when writing the STATUS register. DREIF is cleared by writing DATA.
Atmel AVR XMEGA AU 23.15.3 CTRLA – Control register A Bit 7 6 5 4 3 2 +0x03 – – RXCINTLVL[1:0] Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TXCINTLVL[1:0] 1 0 DREINTLVL[1:0] CTRLA • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU shift register and transmit buffer register do not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port. • Bit 2 – CLK2X: Double Transmission Speed Setting this bit will reduce the divisor of the baud rate divider from16 to 8, effectively doubling the transfer rate for asynchronous communication modes. For synchronous operation, this bit has no effect and should always be written to zero.
Atmel AVR XMEGA AU • Bits 5:4 – PMODE[1:0]: Parity Mode These bits enable and set the type of parity generation according to Table 23-8 on page 313. When enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will generate a parity value for the incoming data and compare it to the PMODE setting, and if a mismatch is detected, the PERR flag in STATUS will be set. These bits are unused in master SPI mode operation. Table 23-8.
Atmel AVR XMEGA AU • Bit 2 – UDORD: Data Order This bit is only for master SPI mode, and this bit sets the frame format. When written to one, the lsb of the data word is transmitted first. When written to zero, the msb of the data word is transmitted first. The receiver and transmitter use the same setting. Changing the setting of UDORD will corrupt all ongoing communication for both receiver and transmitter.
Atmel AVR XMEGA AU 23.16 Register Summary 23.16.1 Register Description - USART Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 BUFOVF PERR – RXB8 – – – – – RXEN TXEN CLK2X MPCM +0x00 DATA +0x01 STATUS RXCIF TXCIF DREIF FERR +0x02 Reserved – – – +0x03 CTRLA – – +0x04 CTRLB – – +0x06 BAUDCTRLA +0x07 BAUDCTRLB CTRLC 23.16.
Atmel AVR XMEGA AU 24. IRCOM - IR Communication Module 24.1 Features • Pulse modulation/demodulation for infrared communication • IrDA compatible for baud rates up to 115.2kbps • Selectable pulse modulation scheme – 3/16 of the baud rate period – Fixed pulse period, 8-bit programmable – Pulse modulation disabled • Built-in filtering • Can be connected to and used by any USART 24.2 Overview XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.
Atmel AVR XMEGA AU For transmission, three pulse modulation schemes are available: • 3/16 of the baud rate period • Fixed programmable pulse time based on the peripheral clock frequency • Pulse modulation disabled For reception, a fixed programmable minimum high-level pulse width for the pulse to be decoded as a logical 0 is used. Shorter pulses will then be discarded, and the bit will be decoded to logical 1 as if no pulse was received. The module can only be used in combination with one USART at a time.
Atmel AVR XMEGA AU 24.3 24.3.1 Registers Description TXPLCTRL – Transmitter Pulse Length Control Register Bit 7 6 5 +0x01 4 3 2 1 0 TXPLCTRL[7:0] TXPLCTRL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – TXPLCTRL[7:0]: Transmitter Pulse Length Control This 8-bit value sets the pulse modulation scheme for the transmitter. Setting this register will have no effect if IRCOM mode is not selected by a USART.
Atmel AVR XMEGA AU • Bit 3:0 – EVSEL [3:0]: Event Channel Selection These bits select the event channel source for the IRCOM receiver according to Table 24-1 on page 319. If event input is selected for the IRCOM receiver, the input from the USART’s RX pin is automatically disabled. Table 24-1. Event channel selection. EVSEL[3:0] Group Configuration 0000 None 0001 (Reserved) 0010 (Reserved) 0011 (Reserved) 0100 (Reserved) 0101 (Reserved) 0110 (Reserved) 0111 (Reserved) 1nnn 24.
Atmel AVR XMEGA AU 25. AES and DES Crypto Engines 25.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) crypto module • DES Instruction – Encryption and decryption – DES supported – Encryption/decryption in 16 CPU clock cycles per 8-byte block • AES crypto module – Encryption and decryption – Supports 128-bit keys – Supports XOR data load mode to the state memory – Encryption/decryption in 375 clock cycles per 16-byte block 25.
Atmel AVR XMEGA AU Figure 25-1. Register file usage during DES encryption/decryption. Register File data R0 data0 R1 data1 R2 data2 R3 data3 R4 data4 R5 data5 R6 data6 R7 data7 R8 key0 key R9 key1 R10 key2 R11 key3 R12 key4 R13 key5 R14 key6 R15 key7 R16 ... R31 Executing one DES instruction performs one round in the DES algorithm. Sixteen rounds must be executed in increasing order to form the correct DES ciphertext or plaintext.
Atmel AVR XMEGA AU The following setup and use procedure is recommended: 1. Enable the AES interrupt (optional). 2. Select the AES direction to encryption or decryption. 3. Load the key data block into the AES key memory. 4. Load the data block into the AES state memory. 5. Start the encryption/decryption operation. If more than one block is to be encrypted or decrypted, repeat the procedure from step 3.
Atmel AVR XMEGA AU Figure 25-3. The key memory with pointers and register. 0 1 4-bit key write address pointer 14 15 4-bit key read address pointer Reset pointer reset or access to CTRL Reset pointer reset or access to CTRL KEY In the AES crypto module, the following definition of the key is used: • In encryption mode, the key is the one defined in the AES standard. • In decryption mode, the key is the last subkey of the expanded key defined in the AES standard.
Atmel AVR XMEGA AU 25.5 25.5.1 Register Description – AES CTRL – Control register Bit 7 6 5 4 3 2 1 0 START AUTO RESET DECRYPT – XOR – – Read/Write R/W R/W R/W R/W R R/W R R Initial Value 0 0 0 0 0 0 0 0 +0x00 CTRL • Bit 7 – START: Start/Run Setting this bit starts the encryption/decryption procedure, and this bit remains set while the encryption/decryption is ongoing. Writing this bit to zero will stop/abort any ongoing encryption/decryption process.
Atmel AVR XMEGA AU • Bit 1:0 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. 25.5.2 STATUS – AES Status register Bit 7 6 5 4 3 2 1 0 ERROR – – – – – – SRIF Read/Write R/W R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 +0x01 STATUS • Bit 7 – ERROR: Error The ERROR flag indicates an illegal handling of the AES crypto module.
Atmel AVR XMEGA AU 25.5.4 KEY – Key register Bit 7 6 5 4 +0x03 3 2 1 0 KEY[7:0] KEY Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The KEY register is used to access the key memory. Before encryption/decryption can take place, the key memory must be written sequentially, byte-by-byte, through the KEY register. After encryption/decryption is done, the last subkey can be read sequentially, byte-by-byte, through the KEY register.
Atmel AVR XMEGA AU 25.6 Register Summary - AES Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page +0x00 CTRL START AUTO RESET DECRYPT – XOR – – 324 +0x01 STATUS ERROR – – – – – – SRIF 325 +0x02 STATE STATE[7:0] +0x03 KEY KEY[7:0] +0x04 INTCTRL – – – – – – +0x05 Reserved – – – – – – – – +0x06 Reserved – – – – – – – – +0x07 Reserved – – – – – – – – 25.
Atmel AVR XMEGA AU 26. CRC – Cyclic Redundancy Check Generator 26.
Atmel AVR XMEGA AU 26.3 Operation The data source for the CRC module must be selected in software as either flash memory, the DMA channels, or the I/O interface. The CRC module then takes data input from the selected source and generates a checksum based on these data. The checksum is available in the CHECKSUM registers in the CRC module. When CRC-32 polynomial is used, the final checksum read is bit reversed and complemented (see Figure 26-1).
Atmel AVR XMEGA AU 26.5 CRC on DMA Data CRC-16 or CRC-32 calculations can be performed on data passing through any DMA channel. Once a DMA channel is selected as the source, the CRC module will continuously generate the CRC on the data passing through the DMA channel. The checksum is available for readout once the DMA transaction is completed or aborted. A CRC can be performed not only on communication data, but also on data in SRAM or I/O memory by passing these data through a DMA channel.
Atmel AVR XMEGA AU 26.7 26.7.1 Register Description CTRL – Control register Bit 7 +0x00 6 RESET[1:0] 5 4 CRC32 – 3 2 1 0 SOURCE[3:0] CTRL Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:6 – RESET[1:0]: Reset These bits are used to reset the CRC module, and they will always be read as zero. The CRC registers will be reset one peripheral clock cycle after the RESET[1] bit is set. Table 26-1. RESET[1:0] CRC reset.
Atmel AVR XMEGA AU Table 26-2. CRC source select (Continued). SOURCE[3:0] 26.7.2 Group configuration Description 0110 DMACH2 DMA controller channel 2 0111 DMACH3 DMA controller channel 3 1xxx — Reserved for future use STATUS – Status register Bit 7 6 5 4 3 2 1 0 +0x02 – – – – – – ZERO BUSY Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 STATUS • Bit 7:2 – Reserved These bits are unused and reserved for future use.
Atmel AVR XMEGA AU 26.7.4 CHECKSUM0 – Checksum Byte 0 CHECKSUM0, CHECKSUM1, CHECKSUM2, and CHECKSUM3 represent the 16- or 32-bit CHECKSUM value and the generated CRC. The registers are reset to zero by default, but it is possible to write RESET to reset all bits to one. It is possible to write these registers only when the CRC module is disabled. If NVM is selected as the source, reading CHECKSUM will return a zero value until the BUSY flag is cleared. If CRC-32 is selected and the BUSY flag is cleared (i.
Atmel AVR XMEGA AU • Bit 7:0 – CHECKSUM[31:24] These bits hold byte 3 of the generated CRC when CRC-32 is used. 26.
Atmel AVR XMEGA AU 27. EBI – External Bus Interface 27.1 Features • Supports SRAM up to: • • • • 27.2 – 512KB using 2-port EBI – 16MB using 3-port EBI Supports SDRAM up to: – 128Mb using 3-port EBI Four software configurable chip selects Software configurable wait state insertion Can run from the 2x peripheral clock frequency for fast access Overview The External Bus Interface (EBI) is used to connect external peripherals and memory for accessthrough the data memory space.
Atmel AVR XMEGA AU 27.3.1 Base Address The base address assigned to a chip select is the lowest address in the address space, and determines the first location in data memory space where the connected memory hardware can be accessed. The base address associated with each chip select must be on a 4KB boundary. Figure 27-1. Base Address ADDRESS[n-1:0] A[n-1:0] ADDRESS[23:n] D[7:0] CS = BASEADDR[23:n] 27.3.
Atmel AVR XMEGA AU 27.4 EBI Clock The EBI is clocked from the Peripheral 2x (ClkPER2) Clock. This clock can run at the CPU Clock frequency, or at two times the CPU Clock frequency. This can be used to lower the EBI access time. Refer to ”System Clock and Clock Options” on page 82 for details the Peripheral 2x Clock and how to configure this. 27.
Atmel AVR XMEGA AU Figure 27-4. Multiplexed SRAM connection using ALE1. D[7:0] D[7:0] A[15:8]/ A[7:0] A[7:0] EBI D ALE1 Q SRAM G A[19:16] A[19:16] 27.5.3 A[15:8] Multiplexing address byte 0 and 2 When address byte 0 (A[7:0]) and address byte 2 (A[23:16) are multiplexed, they are output from the same port, and the ALE2 signal from the device controls the address latch. Figure 27-5. Multiplexed SRAM connection using ALE2.
Atmel AVR XMEGA AU 27.5.5 Address Latches The Address Latch timing and parameter requirements are described in EBI Timing. See the device datasheet characteristics for details. To reduce access time when using multiplexing of address, the ALE signals are only issued when it is required to update the latched address. For instance if address lines A[15:8] are multiplexed with A[7:0] the ALE1 and A[15:8] are only given if any bit in A[15:8] are changed since the last time ALE was set. 27.5.
Atmel AVR XMEGA AU Figure 27-8. Multiplexed SRAM LPC connection using ALE1 and ALE2. A[15:8]/ AD[7:0] D[7:0] D EBI ALE1 Q SRAM A[15:8] G A[19:16] 27.7 A[7:0] G D ALE2 Q A[19:16] SDRAM Configuration Chip Select 3 on the EBI can be configured from SDRAM operation, and the EBI must be configured as a three-port or four-port interface. The SDRAM can be configured for 4-bit or 8-bit data bus, and four-Port interface must be used for 8-bit data bus.
Atmel AVR XMEGA AU Table 27-3. 27.7.2 Supported SDRAM commands. (Continued) AUTO REFRESH Refresh one row of each bank LOAD MODE Load mode register SELF REFRESH Activate self refresh mode Three-Port EBI Configuration When three EBI ports are available, SDRAM can be connected with a three-Port EBI configuration. When this is done only four-bit data bus is available, and any chip select must be controlled from software using a general purpose I/O pin (Pxn). Figure 27-9. Three-Port SDRAM configuration.
Atmel AVR XMEGA AU 27.7.4 Timing The Clock Enable (CKE) signal is required for SDRAM when the EBI is clocked at 2x the CPU clock speed. 27.7.5 Initialization Configuring Chip Select 3 to SDRAM will enable the initialization of the SDRAM. The Load Mode Register command is automatically issued at the end of the initialization. For correct information to be loaded to the SDRAM, one of the following must be done: – 1. Configure the SDRAM control registers before enabling chip select 3 to SDRAM – 2.
Atmel AVR XMEGA AU Figure 27-11. Combined SRAM and SDRAM connection CLK CLK CKE CKE BA[1:0] BA[1:0] DQM DQM WE WE EBI RAS/ALE1 RAS CAS/RE CAS SDRAM D[7:0] D[7:0] A[7:0] A[7:0]/A[15:8] A[11:8] A[11:8]/A[19:16] CS[3:0] CS CS WE RE D[7:0] A[7:0] D Q SRAM A[15:8] G A[19:16] 27.9 I/O Pin and Pin-out Configuration When the EBI is enabled, it will override the direction and/or value of the I/O pins where the EBI data lines are placed.
Atmel AVR XMEGA AU Table 27-4. Pin-out SRAM. PORT PIN PORT3 7:0 PORT2 7:0 PORT1 SRAM 3PORT ALE1 SRAM 4PORT ALE2 SRAM 4PORT NOALE A[15:8] A[15:8] A[7:0]/ A[15:8]/ A[23:16] A[7:0]/ A[7:0] – A[7:0]/ A[15:8] – A[23:16] 7:0 D[7:0] D[7:0] D[7:0] D[7:0] 7:4 CS[3:0] (A[19:16]) CS[3:0] CS[3:0] CS[3:0] (A[21:18]) ALE2 ALE2 – 3 PORT0 SRAM 3PORT ALE12 A17 – ALE1 ALE1 1 RE RE RE RE 0 WE WE WE WE SRAM LPC 3PORT/4PORT ALE1 SRAM 2/3/4PORT ALE12 Table 27-5.
Atmel AVR XMEGA AU Table 27-6. PORT Pin-out for SRAM and SRAM LPC when combined with SDRAM (four-port only).
Atmel AVR XMEGA AU 27.10 Register Description – EBI 27.10.1 CTRL – Control register Bit 7 +0x00 6 SDDATAW[1:0] 5 4 3 LPCMODE[1:0] 2 SRMODE[1:0] 1 0 IFMODE[1:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 CTRL • Bit 7:6 – SDDATAW[1:0]: SDRAM Data Width Setting These bits select the EBI SDRAM data width configuration, according to Table 27-8 on page 346. Table 27-8. SDRAM Mode.
Atmel AVR XMEGA AU • Bit 1:0 – IFMODE[1:0]: Interface Mode These bits select EBI interface mode and the number of ports that should be enabled and overridden for EBI, according to Table 27-11 on page 347. Table 27-11. EBI Mode IFMODE[1:0] 27.10.
Atmel AVR XMEGA AU Table 27-14. SDRAM column bits. SDCOL[1:0] 27.10.
Atmel AVR XMEGA AU • Bit 13:0 – INITDLY[13:0]: SDRAM Initialization Delay This register is used to delay the initialisation sequence after the controller is enabled until all voltages are stabilized and the SDRAM clock has been running long enough to take the SDRAM chip through its initialisation sequence. The initialisation sequence includes pre-charge all banks to their idle state issuing an auto-refresh cycle and then loading the mode register.
Atmel AVR XMEGA AU Table 27-17. SDRAM row to precharge delay settings RPDLY[2:0] 27.10.
Atmel AVR XMEGA AU Table 27-19. SDRAM exit self-refresh delay settings.
Atmel AVR XMEGA AU Table 27-21.
Atmel AVR XMEGA AU 27.11.2 CTRLB (SRAM) – Control register B The configuration options for this register depend on the chip select mode configuration. The register description below is valid when the chip select mode is configured for SRAM or SRAM LPC. Bit 7 6 5 4 3 +0x01 – – – – – 2 1 0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SRWS[2:0] CTRLB • Bit 7:3 – Reserved These bits are unused and reserved for future use.
Atmel AVR XMEGA AU • Bit 1:0 SDMODE[1:0]: SDRAM Mode These bits select the mode when accessing SDRAM according to Table 27-24 on page 354. Table 27-24. SDRAM mode SDMODE[1:0] 27.11.
Atmel AVR XMEGA AU 27.
Atmel AVR XMEGA AU 28. ADC – Analog-to-Digital Converter 28.1 Features • 12-bit resolution • Up to two million samples per second • • • • • • • • • • 28.2 – Two inputs can be sampled simultaneously using ADC and 1x gain stage – Four inputs can be sampled within 1.5µs – Down to 2.5µs conversion time with 8-bit resolution – Down to 3.
Atmel AVR XMEGA AU The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention required. Figure 28-1. ADC overview. VIN S&H ADC Σ VOUT 2x DAC ADC0 Compare 2 bits •• • ADC15 Internal signals ADC0 • • • Stage 1 2 VINP Stage 2 2 Stage 12 2 Digital Correction Logic ADC7 CH0 Result < > Threshold (Int Req) CH1 Result ½x - 64x ADC4 CH2 Result •• • ADC7 Int. signals Internal signals CH3 Result VINN ADC0 • •• ADC3 Int.
Atmel AVR XMEGA AU Figure 28-2. Differential measurement without gain. ADC0 • • • ADC15 + ADC0 • • • ADC3 GND INTGND 28.3.2 - Differential Input with Gain When differential input with gain is enabled, all input pins can be selected as positive input, and input pins 4 to 7 can be selected as negative input. When the gain stage is used, the differential input is first sampled and amplified by the gain stage before the result is fed into the ADC.
Atmel AVR XMEGA AU Figure 28-4. Single-ended measurement in signed mode. ADC0 • • • ADC15 - In unsigned mode, the negative input is connected to half of the voltage reference (VREF) voltage minus a fixed offset. The nominal value for the offset is: ΔV = VREF × 0.05 Since the ADC is differential, the input range is VREF to zero for the positive single-ended input.
Atmel AVR XMEGA AU nal signals is lower than that of the ADC. Refer to the ADC characteristics in the device datasheets for details. For differential measurement Pad Ground (Gnd) and Internal Gnd can be selected as negative input. Pad Gnd is the gnd level on the pin and identical or very close to the external gnd. Internal Gnd is the internal device gnd level. Internal Gnd is used as the negative input when other internal signals are measured in singleended signed mode. Figure 28-6.
Atmel AVR XMEGA AU 28.5 Voltage Reference Selection The following voltages can be used as the reference voltage (VREF) for the ADC: • • • • • Accurate internal 1.00V voltage generated from the bandgap Internal VCC/1.6V voltage Internal VCC/2V voltage External voltage applied to AREF pin on PORTA External voltage applied to AREF pin on PORTB Figure 28-8. ADC voltage reference selection Internal 1.00V Internal VCC/1.6V Internal VCC/2.0V AREFA AREFB 28.
Atmel AVR XMEGA AU can be represented either left or right adjusted. Left adjusted means that the eight most-significant bits (msb) are found in the high byte. When the ADC is in signed mode, the msb represents the sign bit. In 12-bit right adjusted mode, the sign bit (bit 11) is padded to bits 12-15 to create a signed 16-bit number directly. In 8-bit mode, the sign bit (bit 7) is padded to the entire high byte.
Atmel AVR XMEGA AU 28.7 Compare Function The ADC has a built-in 12-bit compare function. The ADC compare register can hold a 12-bit value that represents a threshold voltage. Each ADC channel can be configured to automatically compare its result with this compare value to give an interrupt or event only when the result is above or below the threshold. All four ADC channels share the same compare register. 28.
Atmel AVR XMEGA AU RESOLUTION is the resolution, 8 or 12 bits. The propagation delay will increase by one extra ADC clock cycle if the gain stage (GAIN) is used. The propagation delay is longer than one ADC clock cycle, but the pipelined design means that the sample rate is limited not by the propagation delay, but by the ADC clock rate.
Atmel AVR XMEGA AU Figure 28-14. ADC timing for one single conversion with gain. 1 2 3 4 5 6 7 9 8 CLKADC START GAINSTAGE SAMPLE GAINSTAGE AMPLIFY ADC SAMPLE IF MSB CONVERTING BIT 28.9.3 9 10 7 8 6 5 4 3 2 1 LSB Single Conversions on Two ADC Channels Figure 28-15 on page 365 shows the ADC timing for single conversions on two channels. The pipelined design enables the second conversion to start on the next ADC clock cycle after the first conversion has started.
Atmel AVR XMEGA AU Figure 28-16. ADC timing for single conversion on two ADC channels, CH0 with gain. 1 2 3 4 5 6 7 9 8 10 CLKADC START CH0, w/GAIN START CH1, wo/GAIN GAINSTAGE SAMPLE GAINSTAGE AMPLIFY ADC SAMPLE IF CH0 IF CH1 MSB CONVERTING BIT CH0 10 CONVERTING BIT CH1 28.9.
Atmel AVR XMEGA AU done and available, and so on. In this mode, up to eight conversions are ongoing at the same time. Figure 28-18. ADC timing for free running mode. 1 2 3 4 5 6 7 9 8 10 CLKADC START CH0, wo/GAIN START CH1, wo/GAIN START CH0, w/GAIN START CH1, w/GAIN GAINSTAGE SAMPLE 2 GAINSTAGE AMPLIFY ADC SAMPLE 2 0 2 3 1 2 3 2 3 3 0 CONV COMPLETE 1 3 2 3 0 0 1 28.
Atmel AVR XMEGA AU In order to achieve n bits of accuracy, the source output resistance, Rsource, must be less than the ADC input resistance on a pin: Ts R source ≤ ---------------------------------------------- – R channel – R switch n+1 C sample ⋅ ln ( 2 ) where the ADC sample time, TS is one-half the ADC clock cycle given by: 1 T s ≤ ------------------2 ⋅ f ADC For details on Rchannel, Rswitch, and Csample, refer to the ADC and ADC gain stage electrical characteristic in the device datasheet. 28.10.
Atmel AVR XMEGA AU 28.15 Synchronous Sampling The ADC can be configured to do synchronous sampling in three different ways. 1. Sample two input channels at the same time 2. Sample two ADCs at the same time 3. Sample on external trigger 28.15.1 Synchronous sampling of two ADC inputs The ADC supports sampling of two input channels at the same time. This is achieved by setting up channel n to use 1x gain and channel n+1 to not use gain.
Atmel AVR XMEGA AU 28.16 Register Description – ADC 28.16.1 CTRLA – Control register A Bit 7 +0x00 6 5 4 DMASEL[1:0] 3 2 CHSTART[3:0] 1 0 FLUSH ENABLE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 CTRLA • Bit 7:6 – DMASEL[1:0]: DMA Request Selection To allow one DMA channel to serve more than one ADC channel, the DMA request from the channels can be combined into a common DMA request. See Table 28-1 for details. Table 28-1. DMA request selection.
Atmel AVR XMEGA AU Table 28-2. Gain stage impedance mode. IMPMODE Group Configuration Description 0 HIGHIMP For high-impedance sources; charge will remain on input 1 LOWIMP For low impedance sources • Bit 6:5 – CURRLIMIT[1:0]: Current Limitation These bits can be used to limit the current consumption of the ADC by reducing the maximum ADC sample rate. The available settings are shown in Table 28-3 on page 371. The indicated current limitations are nominal values.
Atmel AVR XMEGA AU 28.16.3 REFCTRL – Reference Control register Bit 7 6 5 +0x02 – Read/Write R R/W R/W Initial Value 0 0 0 4 3 2 1 0 – – BANDGAP TEMPREF R/W R R R/W R/W 0 0 0 0 0 REFSEL[2:0] REFCTRL • Bit 7 – Reserved This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero when this register is written.
Atmel AVR XMEGA AU Table 28-6. ADC channel select. SWEEP[1:0] Group Configuration Active ADC Channels for Channel Sweep 00 0 Only ADC channel 0 01 01 ADC channels 0 and 1 10 012 ADC channels 0, 1, and 2 11 0123 ADC channels 0, 1, 2, and 3 • Bit 5:3 – EVSEL[2:0]: Event Channel Input Select These bits select which event channel will trigger which ADC channel.
Atmel AVR XMEGA AU Table 28-8. ADC event mode select. 101 SWEEP One sweep of all ADC channels defined by SWEEP on incoming event channel with the lowest number defined by EVSEL 110 SYNCSWEEP One sweep of all active ADC channels defined by SWEEP on incoming event channel with the lowest number defined by EVSE. In addition the ADC is flushed and restarted for accurate timing 111 28.16.
Atmel AVR XMEGA AU • Bit 3:0 – CH[3:0]IF: Interrupt Flags These flags are set when the ADC conversion is complete for the corresponding ADC channel. If an ADC channel is configured for compare mode, the corresponding flag will be set if the compare condition is met. CHnIF is automatically cleared when the ADC channel n interrupt vector is executed. The flag can also be cleared by writing a one to its bit location. 28.16.
Atmel AVR XMEGA AU 28.16.10 CHnRESH – Channel n Result Register High The CHnRESL and CHnRESH register pair represents the 16-bit value, CHnRES. For details on reading 16-bit registers, refer to ”Accessing 16-bit Registers” on page 13. Bit 7 6 5 4 12-bit, right – – – – 8-bit – – – – – Read/Write R R R R Initial Value 0 0 0 0 12-bit, left 28.16.10.
Atmel AVR XMEGA AU • Bit 3:0 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. 28.16.12 CMPH – Compare Register High The CMPH and CMPL register pair represents the 16-bit value, CMP. For details on reading and writing 16-bit registers, refer to ”Accessing 16-bit Registers” on page 13.
Atmel AVR XMEGA AU See Table 28-8 on page 373. Gain is valid only with certain MUX settings. See ”MUXCTRL – ADC Channel MUX Control registers” on page 378. Table 28-10. ADC gain factor. GAIN[2:0] Group Configuration Gain Factor 000 1X 1x 001 2X 2x 010 4X 4x 011 8X 8x 100 16X 16x 101 32X 32x 110 64X 64x 111 DIV2 ½x • Bit 1:0 – INPUTMODE[1:0]: Channel Input Mode These bits define the channel mode. Changing input mode will corrupt any data in the pipeline. Table 28-11.
Atmel AVR XMEGA AU • Bit 6:3 – MUXPOS[3:0]: MUX Selection on Positive ADC Input These bits define the MUX selection for the positive ADC input. Table 28-13 on page 379 and Table 28-14 on page 379 show the possible input selection for the different input modes. Table 28-13. ADC MUXPOS configuration when INPUTMODE[1:0] = 00 (internal) is used.
Atmel AVR XMEGA AU Table 28-15. ADC MUXPOS configuration when INPUTMODE[1:0] = 11 (differential with gain) is used. (Continued) 0100 PIN4 ADC4 pin 0101 PIN5 ADC5 pin 0110 PIN6 ADC6 pin 0111 PIN7 ADC7 pin 1XXX Reserved Depending on the device pin count and feature configuration, the actual number of analog input pins may be less than 16. Refer to the device datasheet and pin-out description for details.
Atmel AVR XMEGA AU 28.17.3 INTCTRL – Channel Interrupt Control registers Bit 7 6 5 4 3 2 1 INTMODE[1:0} 0 +0x02 – – – – Read/Write R R R R R/W R/W R/W INTLVL[1:0] R/W INTCTRL Initial Value 0 0 0 0 0 0 0 0 • Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU The RESL and RESH register pair represents the 16-bit value, ADCRESULT. Reading and writing 16-bit values require special attention. Refer to ”Accessing 16-bit Registers” on page 13 for details. Bit 7 6 5 4 12-bit, left. 12-bit, right +0x05 2 1 0 – – – – – – – – – – – – Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 8-bit 28.17.5.
Atmel AVR XMEGA AU • Bit 3:0 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. 28.17.7 SCAN – Channel Scan register Scan is enabled when COUNT is set differently than 0. This register is available only for ADC channel 0.
Atmel AVR XMEGA AU 28.18 Register Summary – ADC This is the register summary when the ADC is configured to give standard 12-bit results. The register summaries for 8-bit and 12-bit left adjusted will be similar, but with some changes in the result registers, CHnRESH and CHnRESL.
Atmel AVR XMEGA AU 28.20 Interrupt vector Summary Table 28-19. Analog-to-digital converter interrupt vectors and their word offset address.
Atmel AVR XMEGA AU 29. DAC – Digital to Analog Converter 29.1 Features • • • • • • • • • • 29.
Atmel AVR XMEGA AU A DAC conversion is automatically started when new data to be converted are available. Events from the event system can also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and other peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the DAC. The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, aswell as loads which combine both.
Atmel AVR XMEGA AU Figure 29-2. DAC output model R feedback DAC voltage Buffer DAC out DAC output R channel 29.7 DAC clock The DAC is clocked directly from the peripheral clock (clkPER), and this puts a limitation on how fast new data can be clocked into the DAC data registers. 29.8 Low Power mode To reduce the power consumption in DAC conversions, the DAC may be set in a Low Power mode. Conversion time will be longer if new conversions are started in this mode.
Atmel AVR XMEGA AU Equation 29-3.Gain calibration. VREF GCAL [ 6 ] GCAL [ 5 ] GCAL [ 4 ] GCAL [ 3 ] GCAL [ 2 ] GCAL [ 1 ] GCAL [ 0 ] V GCAL = ( V DAC – ⎛⎝ ---------------⎞⎠ ⎞⎠ ⋅ ( 1 – 2.
Atmel AVR XMEGA AU 29.10 Register Description 29.10.1 CTRLA – Control Register A Bit 7 6 5 4 3 2 1 0 +0x00 – – – IDOEN CH1EN CH0EN LPMODE ENABLE Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 CTRLA • Bit 7:5 – Reserved These bite are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU Table 29-1. DAC channel selection CHSEL[1:0] Group Configuration Description 00 SINGLE Single-channel operation on channel 0 01 SINGLE1 Single-channel operation on channel 1 10 DUAL Dual-channel operation 11 – Reserved • Bit 4:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU • Bit 0 - LEFTADJ: Left-Adjust Value If this bit is set, CH0DATA and CH1DATA are left-adjusted. 29.10.4 EVCTRL – Event Control Register Bit 7 6 5 4 3 2 1 0 +0x03 – – – – Read/Write R R R R R/W R/W EVSEL[3:0] R/W R/W EVCTRL Initial Value 0 0 0 0 0 0 0 0 • Bit 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU • Bit 1 – CH1DRE: Channel 1 Data Register Empty This bit when set indicates that the data register for channel 1 is empty, meaning that a new conversion value may be written. Writing to the data register when this bit is cleared will cause the pending conversion data to be overwritten. This bit is directly used for DMA requests.
Atmel AVR XMEGA AU 29.10.7 CH0DATAL – Channel 0 Data Register Low Bit 7 6 5 4 Right-adjust 3 2 1 0 CHDATA[7:0] +0x18 Left-adjust 29.10.7.
Atmel AVR XMEGA AU 29.10.9 CH1DATAL – Channel 1 Data Register Low Bit 7 6 5 4 Right-adjust 3 2 1 0 CHDATA[7:0] +0x1A Left-adjust 29.10.9.
Atmel AVR XMEGA AU 29.10.12 CH1GAINCAL – Gain Calibration Register Bit 7 6 5 +0x0A 4 3 2 1 0 CH1GAINCAL[7:0] CH1GAINCAL Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – CH0GAINCAL[7:0]: Gain Calibration value These bits are used to compensate for the gain error in DAC channel 1. See ”Calibration” on page 388 for details. 29.10.
Atmel AVR XMEGA AU 29.11 Register Summary This is the I/O summary when the DAC is configured to give standard 12-bit results. The I/O summary for 12-bit left-adjusted results will be similar, but with some changes in the CHnDATAL and CHnDATAH data registers.
Atmel AVR XMEGA AU 30. AC – Analog Comparator 30.1 Features • Selectable propagation delay versus current consumption • Selectable hysteresis • • • • • 30.
Atmel AVR XMEGA AU Figure 30-1. Analog comparator overview. Pin Input + AC0OUT Pin Input Hysteresis DAC Enable Interrupt Mode Voltage Scaler ACnCTRL ACnMUXCTRL WINCTRL Interrupt Sensititivity Control & Window Function Interrupts Events Enable Bandgap Hysteresis + Pin Input AC1OUT Pin Input 30.3 Input Sources Each analog comparator has one positive and one negative input. Each input may be chosen from a selection of analog input pins and internal inputs such as a VCC voltage scaler.
Atmel AVR XMEGA AU (falling edge). Events are generated at all times for the same condition as the interrupt, regardless of whether the interrupt is enabled or not. 30.6 Window Mode Two analog comparators on the same port can be configured to work together in window mode. In this mode, a voltage range is defined, and the analog comparators give information about whether an input signal is within this range or not. Figure 30-2. The Analog comparators in window mode.
Atmel AVR XMEGA AU 30.9 30.9.1 Register Description ACnCTRL – Analog Comparator n Control register Bit 7 +0x00 / +0x01 6 5 INTMODE[1:0] 4 INTLVL[1:0] 3 HSMODE 2 1 HYSMODE[2:0] 0 ENABLE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ACnCTRL • Bit 7:6 – INTMODE[1:0]: Interrupt Modes These bits configure the interrupt mode for analog comparator n according to Table 30-1. Table 30-1. Interrupt settings.
Atmel AVR XMEGA AU 30.9.2 ACnMUXCTRL – Analog Comparator n Mux Control register Bit 7 6 5 4 3 2 +0x02 / +0x03 – – Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MUXPOS[2:0] 1 0 MUXNEG[2:0] ACnMUXCTRL • Bit 7:6 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written.
Atmel AVR XMEGA AU 30.9.3 CTRLA – Control register A Bit 7 6 5 4 3 2 1 0 +0x04 – – – – – – AC1OUT AC0OUT Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 CTRLA • Bit 7:2 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 1 – AC1OUT: Analog Comparator 1 Output Setting this bit makes the output of AC1 available on pin 6 of the port.
Atmel AVR XMEGA AU • Bits 3:2 – WINTMODE[1:0]: Window Interrupt Mode Settings These bits configure the interrupt mode for the analog comparator window mode according to Table 30-5. Table 30-5. Window mode interrupt settings.
Atmel AVR XMEGA AU This flag is automatically cleared when the analog comparator window interrupt vector is executed. The flag can also be cleared by writing a one to its bit location. • Bit 1 – AC1IF: Analog Comparator 1 Interrupt Flag This is the interrupt flag for AC1. AC1IF is set according to the INTMODE setting in the corresponding ”ACnCTRL – Analog Comparator n Control register” on page 401. This flag is automatically cleared when the analog comparator 1 interrupt vector is executed.
Atmel AVR XMEGA AU • Bits 7:4 – Reserved These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero when this register is written. • Bit 3:0 – CALIB[3:0]: Current Source Calibration The constant current source is calibrated during production. A calibration value can be read from the signature row and written to the CURRCALIB register from software. Refer to device data sheet for default calibration values and user calibration range.
Atmel AVR XMEGA AU 30.
Atmel AVR XMEGA AU 31. IEEE 1149.1 JTAG Boundary Scan Interface 31.1 Features • • • • • • 31.2 JTAG (IEEE Std. 1149.
Atmel AVR XMEGA AU • TDI: Test data in. Serial input data to be shifted in to the instruction register or data register (scan chains) • TDO: Test data out. Serial output data from the instruction register or data register The IEEE Std. 1149.1-2001 also specifies an optional test reset signal, TRST. This signal is not available. When the JTAGEN fuse is unprogrammed or the JTAG disable bit is set, the JTAG interface is disabled. The four TAP pins are normal port pins, and the TAP controller is in reset.
Atmel AVR XMEGA AU TDO pin. The JTAG instruction selects a particular data register as the path between TDI and TDO and controls the circuitry surrounding the selected data register • Apply the TMS sequence 1, 1, 0 to reenter the run test/idle state. The instruction is latched onto the parallel output from the shift register path in the update IR state.
Atmel AVR XMEGA AU The active states are: • Capture DR: Data in the IDCODE register are sampled into the device identification register • Shift DR: The IDCODE scan chain is shifted by the TCK input 31.4.3 SAMPLE/PRELOAD; 0x2 SAMPLE/PRELOAD is the instruction for preloading the output latches and taking a snapshot of the input/output pins without affecting system operation. However, the output latches are not connected to the pins. The boundary scan chain is selected as the data register.
Atmel AVR XMEGA AU The active states are: • Capture DR: Parallel data from the PDI are sampled into the PDICOM data register • Shift DR: The PDICOM data register is shifted by the TCK input • Update DR: Commands or operands are parallel-latched from the PDICOM data register into the PDI 31.5 Boundary Scan Chain The boundary scan chain has the capability of driving and observing the logic levels on the I/O pins.
Atmel AVR XMEGA AU 31.5.2 Scanning the PDI Pins Two observe-only cells are inserted to make the combined RESET and PDI_CLK pin and the PDI_DATA pin observable. Even though the PDI_DATA pin is bidirectional, it is only made observable in order to avoid any extra logic on the PDI_DATA output path. Figure 31-3. An observe-only input cell. To next cell To system logic From system pin 0 D Q 31.
Atmel AVR XMEGA AU 31.6.1 Bypass Register The bypass register consists of a single shift register stage. When the bypass register is selected as the path between TDI and TDO, the register is reset to 0 when leaving the capture DR controller state. The bypass register can be used to shorten the scan chain on a system when the other devices are to be tested. 31.6.2 Device Identification Register Figure 31-5. Device identification register. MSB Bit Device ID 31.6.2.
Atmel AVR XMEGA AU 32. Program and Debug Interface 32.
Atmel AVR XMEGA AU 1149.1 compliant, and supports boundary scan. Any external programmer or on-chip debugger/emulator can be directly connected to either of these interfaces. Unless otherwise stated, all references to the PDI assume access through the PDI physical layer. Figure 32-1. The PDI with JTAG and PDI physical layers and closely related modules (grey). PDIBUS Program and Debug Interface (PDI) OCD TDI TMI TCK TDO JTAG Physical (physical layer) PDI Controller PDI_CLK PDI_DATA 32.
Atmel AVR XMEGA AU 32.3.1 Enabling The PDI physical layer must be enabled before use. This is done by first forcing the PDI_DATA line high for a period longer than the equivalent external reset minimum pulse width (refer to device datasheet for external reset pulse width data). This will disable the RESET functionality of the Reset pin, if not already disabled by the fuse settings. Next, continue to keep the PDI_DATA line high for 16 PDI_CLK cycles.
Atmel AVR XMEGA AU Three different characters are used, DATA, BREAK, and IDLE. The BREAK character is equal to a 12-bit length of low level. The IDLE character is equal to a 12- bit length of high level. The BREAK and IDLE characters can be extended beyond the 12-bit length. Figure 32-5. Characters and timing for the PDI physical layer. 1 DATA character START 0 1 2 3 4 5 6 7 P STOP 1 BREAK character BREAK 1 IDLE character IDLE 32.3.
Atmel AVR XMEGA AU 32.3.6 Serial Reception When a start bit is detected, the receiver starts to collect the eight data bits. If the parity bit does not correspond to the parity of the data bits, a parity error has occurred. If one or both of the stop bits are low, a frame error has occurred. If the parity bit is correct, and no frame error is detected, the received data bits are available for the PDI controller.
Atmel AVR XMEGA AU Figure 32-8. Driving data out on the PDI_DATA using a bus keeper. PDI_CLK Output enable PDI Output PDI_DATA 1 0 1 1 0 1 0 If the programmer and the PDI both drive the PDI_DATA line at the same time, drive contention will occur, as illustrated in Figure 32-9 on page 420. Every time a bit value is kept for two or more clock cycles, the PDI is able to verify that the correct bit value is driven on the PDI_DATA line.
Atmel AVR XMEGA AU instruction is shifted into the JTAG instruction register, the JTAG interface can be used to access the PDI for external programming and on-chip debugging. 32.4.2 Disabling The JTAG interface can be disabled by unprogramming the JTAGEN fuse or by setting the JTAG disable bit in the MCU control register from the application code. 32.4.3 32.4.3.
Atmel AVR XMEGA AU Figure 32-11. Special data characters. 1 BREAK CHARACTER (BB+P1) 1 1 0 1 1 1 0 1 P1 1 P1 1 P1 1 DELAY CHARACTER (DB+P1) 1 1 0 1 1 0 1 1 EMPTY CHARACTER (EB+P1) 1 32.4.5 1 0 1 0 1 1 Serial transmission and reception The JTAG interface supports full-duplex communication. At the same time as input data is shifted in on the TDI pin, output data is shifted out on the TDO pin. However, PDI communication relies on half-duplex data transfer.
Atmel AVR XMEGA AU If the PDI is in TX- mode (as a response to an LD instruction), but no transmission request from the PDI controller is pending when the TAP controller enters the capture DR state, a DELAY byte (0xDB) will be loaded into the shift register, and the parity bit will be set (forcing a parity error) when data is shifted out in the shift DR state. This situation occurs during data transmission if the data to be transmitted is not yet available.
Atmel AVR XMEGA AU 32.5.1 Switching between PDI and JTAG modes The PDI controller uses either the JTAG or PDI physical layer for establishing a connection to the programmer. Based on this, the PDI is in either JTAG or PDI mode. When one of the modes is entered, the PDI controller registers will be initialized, and the correct clock source will be selected. The PDI mode has higher priority than the JTAG mode.
Atmel AVR XMEGA AU Due to this mechanism, the programmer can always synchronize the protocol by transmitting two successive BREAK characters. 32.5.5 Reset Signalling Through the reset register, the programmer can issue a reset and force the device into reset. After clearing the reset register, reset is released, unless some other reset source is active. 32.5.6 Instruction Set The PDI has a small instruction set used for accessing both the PDI itself and the internal interfaces.
Atmel AVR XMEGA AU address - and data access. Four different address/data sizes are supported; byte, word, 3 bytes, and long (4 bytes). Multiple-bytes access is internally broken down to repeated single-byte accesses, but it reduces the protocol overhead. 32.5.6.5 LDCS - Load Data from PDI Control and Status Register Space The LDCS instruction is used to load data from the PDI control and status registers into the physical layer shift register for serial read out.
Atmel AVR XMEGA AU Figure 32-14. PDI instruction set summary. Cmd Size A LDS 0 0 0 0 STS 0 1 0 0 Cmd Ptr LD 0 0 1 0 ST 0 1 1 0 Size B Size A/B 1 0 0 0 STCS 1 1 0 0 Ptr - Pointer access (indirect access) 0 0 *(ptr) 0 1 *(ptr++) 1 0 ptr 1 1 ptr++ - Reserved Size B REPEAT KEY 32.
Atmel AVR XMEGA AU addressing is based on an address already stored in the pointer register prior to the access itself. Indirect data access can be optionally combined with pointer register post-increment. The indirect access mode has an option that makes it possible to load or read the pointer register without accessing any other registers. Any register update is performed in a little-endian fashion.
Atmel AVR XMEGA AU 32.7 Register Description – PDI Control and Status Registers The PDI control and status registers are accessible in the PDI control and status register space (CSRS) using the LDCS and STCS instructions. The CSRS contains registers directly involved in configuration and status monitoring of the PDI itself. 32.7.
Atmel AVR XMEGA AU • Bit 2:0 – GUARDTIME[2:0]: Guard Time These bits specify the number of IDLE bits of guard time that are inserted in between PDI reception and transmission direction changes. The default guard time is 128 IDLE bits, and the available settings are shown in Table 32-1 on page 430. In order to speed up the communication, the guard time should be set to the lowest safe configuration accepted. No guard time is inserted when switching from TX to RX mode. Table 32-1. 32.8 Guard time settings.
Atmel AVR XMEGA AU 33. Memory Programming 33.1 Features • Read and write access to all memory spaces from • • • • 33.
Atmel AVR XMEGA AU The device can be locked to prevent reading and/or writing of the NVM. There are separate lock bits for external programming access and self-programming access to the boot loader section, application section, and application table section. 33.3 NVM Controller Access to the nonvolatile memories is done through the NVM controller.
Atmel AVR XMEGA AU This ensures that the given command is executed and the operations finished before the start of a new operation. The external programmer or application software must ensure that the NVM is not addressed when it is busy with a programming operation.
Atmel AVR XMEGA AU selected page buffer location to tag them. When performing an EEPROM page erase, the actual value of the tagged location does not matter. The EEPROM page buffer is automatically erased after: • A system reset • Executing the write EEPROM page command • Executing the erase and write EEPROM page command • Executing the write lock bit and write fuse commands 33.
Atmel AVR XMEGA AU Alternative 1: • Fill the EEPROM page buffer with the selected number of bytes • Perform a EEPROM page erase • Perform a EEPROM page write Alternative 2: • Fill the EEPROM page buffer with the selected number of bytes • Perform an atomic EEPROM page erase and write 33.8 Protection of NVM To protect the flash and EEPROM memories from write and/or read, lock bits can be set to restrict access from external programmers and the application software.
Atmel AVR XMEGA AU out the program memory code. It has the capability to write into the entire flash, including the boot loader section. The boot loader can thus modify itself, and it can also erase itself from the flash if the feature is not needed anymore. 33.11.1.1 Application and Boot Loader Sections The application and boot loader sections in the flash are different when it comes to selfprogramming.
Atmel AVR XMEGA AU Figure 33-1. Flash addressing for self-programming. PAGEMSB BIT WORDMSB FPAGE Z-Pointer 1 FWORD 0 0/1 Low/High Byte select for (E)LPM WORD ADDRESS WITHIN A PAGE PAGE ADDRESS WITHIN THE FLASH FPAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD 00 FWORD 00 01 01 02 02 PAGEEND FLASHEND 33.11.2 NVM Flash Commands The NVM commands that can be used for accessing the flash program memory, signature row and calibration row are listed in Table 33-2.
Atmel AVR XMEGA AU Table 33-2. Flash self-programming commands (Continued).
Atmel AVR XMEGA AU 33.11.2.3 Load Flash Page Buffer The load flash page buffer command is used to load one word of data into the flash page buffer. 1. Load the NVM CMD register with the load flash page buffer command. 2. Load the Z-pointer with the word address to write. 3. Load the data word to be written into the R1:R0 registers. 4. Execute the SPM instruction. The SPM instruction is not protected when performing a flash page buffer load. Repeat step 2-4 until the complete flash page buffer is loaded.
Atmel AVR XMEGA AU In order to use the flash range CRC command, all the boot lock bits must be unprogrammed (no locks). The command execution will be aborted if the boot lock bits for an accessed location are set. 33.11.2.7 Erase Application Section The erase application command is used to erase the complete application section. 1. Load the Z-pointer to point anywhere in the application section. 2. Load the NVM CMD register with the erase application section command 3. Execute the SPM instruction.
Atmel AVR XMEGA AU 1. Load the Z-pointer with the flash page to write. The page address must be written to FPAGE. Other bits in the Z-pointer will be ignored during this operation. 2. Load the NVM CMD register with the erase and write application section/boot loader section page command. 3. Execute the SPM instruction. This requires the timed CCP sequence during selfprogramming. The BUSY flag in the NVM STATUS register will be set until the operation is finished.
Atmel AVR XMEGA AU 1. Load the Z-pointer with the byte address to read. 2. Load the NVM CMD register with the read user signature row / calibration row command 3. Execute the LPM instruction. The destination register will be loaded during the execution of the LPM instruction. To ensure that LPM for reading flash will be executed correctly it is adviced to disable interrupt while using either of these commands. 33.11.
Atmel AVR XMEGA AU 2. Load the NVM CMD register with the read fuses command. 3. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence during self-programming. The result will be available in the NVM DATA0 register. The CPU is halted during the complete execution of the command. 33.11.4 33.11.4.1 EEPROM Programming The EEPROM can be read and written from application code in any part of the flash. Its is both byte and page accessible.
Atmel AVR XMEGA AU When EEPROM memory mapping is enabled, loading a data byte into the EEPROM page buffer can be performed through direct or indirect store instructions. Only the least-significant bits of the EEPROM address are used to determine locations within the page buffer, but the complete memory mapped EEPROM address is always required to ensure correct address mapping. Reading from the EEPROM can be done directly using direct or indirect load instructions.
Atmel AVR XMEGA AU 33.11.5.2 Erase EEPROM Page Buffer The erase EEPROM page buffer command is used to erase the EEPROM page buffer. 1. Load the NVM CMD register with the erase EEPROM buffer command. 2. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence during self-programming. The BUSY flag in the NVM STATUS register will be set until the operation is finished. 33.11.5.3 Erase EEPROM Page The erase EEPROM page command is used to erase one EEPROM page. 1.
Atmel AVR XMEGA AU The BUSY flag in the NVM STATUS register will be set until the operation is finished. 33.11.5.7 Read EEPROM The read EEPROM command is used to read one byte from the EEPROM. 1. Load the NVM CMD register with the read EEPROM command. 2. Load the NVM ADDR register with the address to read. 3. Set the CMDEX bit in the NVM CTRLA register. This requires the timed CCP sequence during self-programming. The data byte read will be available in the NVM DATA0 register. 33.
Atmel AVR XMEGA AU Figure 33-3. Memory map for PDI accessing the data and program memories.
Atmel AVR XMEGA AU data registers, but the NVM controller must be loaded with the correct command (i.e., to read from any NVM, the controller must be loaded with the NVM read command before loading data from the PDIBUS address space). For the reminder of this section, all references to reading and writing data or program memory addresses from the PDI refer to the memory map shown in Figure 33-3 on page 447. The PDI uses byte addressing, and hence all memory addresses must be byte addresses.
Atmel AVR XMEGA AU Change Protected CMD[6:0] Commands / Operation Trigger NVM Busy 0x38 Application section CRC CMDEX Y Y Boot Loader Section 0x68 Erase boot section PDI write N Y 0x2A Erase boot loader section page PDI write N Y 0x2C Write boot loader section page PDI write N Y 0x2D Erase and write boot loader section page PDI write N Y 0x39 Boot loader section CRC NVMAA Y Y Calibration and User Signature Sections 0x01 Read user signature row PDI read N N 0x18 Erase
Atmel AVR XMEGA AU 1. Load the NVM CMD register with the read NVM command. 2. Read the selected memory address by executing a PDI read operation. Dedicated read EEPROM, read fuse, read signature row, and read calibration row commands are also available for the various memory sections. The algorithm for these commands are the same as for the read NVM command. 33.12.3.3 Erase Page Buffer The erase flash page buffer and erase EEPROM page buffer commands are used to erase the flash and EEPROM page buffers. 1.
Atmel AVR XMEGA AU 33.12.3.7 Erase and Write Page The erase and write application section page, erase and write boot loader section page, and erase and write EEPROM page commands are used to erase one page and then write a loaded flash/EEPROM page buffer into that page in the selected memory space in one atomic operation. 1. Load the NVM CMD register with erase and write application section/boot loader section/user signature row/EEPROM page command. 2. Write the selected page by doing a PDI write.
Atmel AVR XMEGA AU 33.13 Register Description Refer to ”Register Description – NVM Controller” on page 26 for a complete register description of the NVM controller. Refer to ”Register Description – PDI Control and Status Registers” on page 429 for a complete register description of the PDI. 33.14 Register Summary Refer to ”Register Description – NVM Controller” on page 26 for a complete register summary of the NVM controller.
Atmel AVR XMEGA AU 34. Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA. All peripherals and modules are not present in all XMEGA devices, refer to device data sheet for the peripherals module address map for a specific device. Table 34-1. Peripheral module address map.
Atmel AVR XMEGA AU Base address Name Description Page 0x0380 ACA Analog comparator pair on port A 0x0390 ACB Analog comparator pair on port B 0x0400 RTC Real time counter 226 0x0420 RTC32 32-bit Real time counter 234 0x0440 EBI External bus interface 355 0x0480 TWIC Two wire interface on port C 0x0490 TWID Two wire interface on port D 0x04A0 TWIE Two wire interface on port E 0x04B0 TWIF Two wire interface on port F 0x04C0 USB USB device 0x0600 PORTA Port A 0x0620 POR
Atmel AVR XMEGA AU Base address Name Description Page 0x09A0 USARTD0 USART 0 on port D 0x09B0 USARTD1 USART 1 on port D 0x09C0 SPID Serial peripheral interface on port D 0x0A00 TCE0 Timer/counter 0 on port E 0x0A40 TCE1 Timer/counter 1 on port E 0x0A80 AWEXE Advanced waveform extensionon port E 216 0x0A90 HIRESE High resolution extension on port E 218 0x0AA0 USARTE0 USART 0 on port E 0x0AB0 USARTE1 USART 1 on port E 0x0AC0 SPIE Serial peripheral interface on port E 0x0B00
Atmel AVR XMEGA AU 35.
Atmel AVR XMEGA AU Mnemonics Operands Description RCALL k Relative Call Subroutine Operation Flags #Clocks PC ← PC + k + 1 None 2 / 3(1) ICALL Indirect Call to (Z) PC(15:0) PC(21:16) ← ← Z, 0 None 2 / 3(1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16) ← ← Z, EIND None 3(1) call Subroutine PC ← k None 3 / 4(1) RET Subroutine Return PC ← STACK None 4 / 5(1) RETI Interrupt Return PC ← STACK I 4 / 5(1) if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CALL
Atmel AVR XMEGA AU Mnemonics Operands Description MOVW Rd, Rr Copy Register Pair LDI Rd, K Load Immediate Operation Flags #Clocks 1 Rd+1:Rd ← Rr+1:Rr None Rd ← K None 1 LDS Rd, k Load Direct from data space Rd ← (k) None 2 LD Rd, X Load Indirect Rd ← (X) None 1(1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X ← ← (X) X+1 None 1(1)(2) LD Rd, -X Load Indirect and Pre-Decrement X ← X - 1, Rd ← (X) ← ← X-1 (X) None 2(1)(2) LD Rd, Y Load Indirect Rd ←
Atmel AVR XMEGA AU Mnemonics Operands Description ELPM Rd, Z+ Extended Load Program Memory and PostIncrement SPM Operation Flags #Clocks Rd Z ← ← (RAMPZ:Z), Z+1 None 3 Store Program Memory (RAMPZ:Z) ← R1:R0 None - (RAMPZ:Z) Z ← ← R1:R0, Z+2 None - Rd ← I/O(A) None 1 I/O(A) ← Rr None 1 STACK ← Rr None 1(1) SPM Z+ Store Program Memory and Post-Increment by 2 IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd
Atmel AVR XMEGA AU Mnemonics Operands Description Operation Flags #Clocks Z ← 0 Z 1 Global Interrupt Enable I ← 1 I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S 1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Two’s Complement Overflow V ← 1 V 1 CLV Clear Two’s Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T 1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1 H 1 CLH Clear Half Carr
Atmel AVR XMEGA AU 36. Appendix A: EBI Timing Diagrams 36.1 SRAM 3-Port ALE1 CS Figure 36-1. Write, no ALE Write, no ALE ClkPER2 CS WE RE ALE1 D[7:0] D[7:0] A[7:0]/A[15:8] A[7:0] Figure 36-2.
Atmel AVR XMEGA AU Figure 36-3. Read, no ALE Read, no ALE Clk PER2 CS WE RE ALE1 D[7:0] D[7:0] A[7:0]/A[15:8] A[7:0] Figure 36-4.
Atmel AVR XMEGA AU 36.2 SRAM 3-Port ALE12 CS Figure 36-5. Write, no ALE Write, no ALE ClkPER2 CS WE RE ALE1 ALE2 D[7:0] D[7:0] A[7:0]/A[15:8]/A[23:16] A[7:0] Figure 36-6.
Atmel AVR XMEGA AU Figure 36-7. Write, ALE1 + ALE2 Write, ALE1 + ALE2 ClkPER2 CS WE RE ALE1 ALE2 D[7:0] A[7:0]/A[15:8]/A[23:16] D[7:0] A[23:16] A[15:8] A[7:0] Figure 36-8.
Atmel AVR XMEGA AU Figure 36-9. Read, ALE1 Read, ALE1 ClkPER2 CS WE RE ALE1 ALE2 D[7:0] D[7:0] A[7:0]/A[15:8]/A[23:16] A[15:8] A[7:0] Figure 36-10.
Atmel AVR XMEGA AU 36.3 SRAM 4-Port ALE2 CS Figure 36-11. Write, no ALE Write, no ALE ClkPER2 CS WE RE ALE2 D[7:0] D[7:0] A[7:0]/A[23:16] A[7:0] A[15:8] A[15:8] Figure 36-12.
Atmel AVR XMEGA AU Figure 36-13. Read, no ALE Read, no ALE ClkPER2 CS WE RE ALE2 D[7:0] D[7:0] A[7:0]/A[23:16] A[7:0] A[15:8] A[15:8] Figure 36-14.
Atmel AVR XMEGA AU 36.4 SRAM 4- Port NOALE CS Figure 36-15. Write Write ClkPER2 CS WE RE D[7:0] D[7:0] A[7:0] A[7:0] A[15:8] A[15:8] A[17:16] A[17:16] Figure 36-16.
Atmel AVR XMEGA AU 36.5 LPC 2- Port ALE12 CS Figure 36-17. Write, ALE1 Write, ALE1 ClkPER2 CS WE RE ALE1 ALE2 D[7:0]/A[7:0]/A[15:8] A[7:0] D[7:0] Figure 36-18.
Atmel AVR XMEGA AU Figure 36-19. Read, ALE1 Read, ALE1 ClkPER2 CS WE RE ALE1 ALE2 D[7:0]/A[7:0]/A[15:8] A[7:0] D[7:0] Figure 36-20.
Atmel AVR XMEGA AU 36.6 LPC 3- Port ALE1 CS Figure 36-21. Write Write ClkPER2 CS WE RE ALE1 D[7:0]/A[7:0] A[7:0] A[15:8] D[7:0] A[15:8] Figure 36-22.
Atmel AVR XMEGA AU 36.7 LPC 2- Port ALE1 CS Figure 36-23. Write Write ClkPER2 CS WE RE ALE1 D[7:0]/A[7:0] A[7:0] D[7:0] Figure 36-24.
Atmel AVR XMEGA AU 36.8 SRAM 3- Port ALE1 no CS Figure 36-25. Write, no ALE Write, no ALE ClkPER2 WE RE ALE1 D[7:0] D[7:0] A[7:0]/A[15:8] A[7:0] A[19:16] A[19:16] Figure 36-26.
Atmel AVR XMEGA AU Figure 36-27. Read, no ALE Read, no ALE ClkPER2 WE RE ALE1 D[7:0] D[7:0] A[7:0]/A[15:8] A[7:0] A[19:16] A[19:16] Figure 36-28.
Atmel AVR XMEGA AU 36.9 SRAM 4- Port NOALE no CS Figure 36-29. Write Write ClkPER2 WE RE D[7:0] D[7:0] A[7:0] A[7:0] A[15:8] A[15:8] A[17:16] A[17:16] A[21:18] A[21:18] Figure 36-30.
Atmel AVR XMEGA AU 36.10 LPC 2- Port ALE12 no CS Figure 36-31. Write, ALE1 Write, ALE1 ClkPER2 CS WE RE ALE1 ALE2 D[7:0]/A[7:0]/A[15:8] A[7:0] D[7:0] Figure 36-32.
Atmel AVR XMEGA AU Figure 36-33. Read, ALE1 Read, ALE1 ClkPER2 CS WE RE ALE1 ALE2 D[7:0]/A[7:0]/A[15:8] A[7:0] D[7:0] Figure 36-34.
Atmel AVR XMEGA AU 36.11 SDRAM init Figure 36-35.
Atmel AVR XMEGA AU 36.12 SDRAM 8-bit Write Figure 36-36.
Atmel AVR XMEGA AU Figure 36-37.
Atmel AVR XMEGA AU Figure 36-38.
Atmel AVR XMEGA AU Figure 36-39.
Atmel AVR XMEGA AU 36.13 SDRAM 8-bit read Figure 36-40.
Atmel AVR XMEGA AU Figure 36-41.
Atmel AVR XMEGA AU Figure 36-42.
Atmel AVR XMEGA AU Figure 36-43.
Atmel AVR XMEGA AU 36.14 SDRAM 4-bit write Figure 36-44.
Atmel AVR XMEGA AU Figure 36-45.
Atmel AVR XMEGA AU Figure 36-46.
Atmel AVR XMEGA AU Figure 36-47.
Atmel AVR XMEGA AU 36.15 SDRAM 4-bit read Figure 36-48.
Atmel AVR XMEGA AU Figure 36-49.
Atmel AVR XMEGA AU Figure 36-50.
Atmel AVR XMEGA AU 36.16 SRAM refresh Figure 36-52.
Atmel AVR XMEGA AU Figure 36-53.
Atmel AVR XMEGA AU Figure 36-54.
Atmel AVR XMEGA AU Figure 36-55.
Atmel AVR XMEGA AU 37. Datasheet Revision History Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. 37.1 8331B – 03/12 1. Added Table 2-1 ”XMEGA AU feature summary overview.” on page 5. 2. Updated ”LOCKBITS – Lock Bit register” on page 35. Description of Bit[1:0] updated and added a table note. 3. Title of Table 4-12 on page 37 changed to “Lock bit protection mode.” 4.
Atmel AVR XMEGA AU 37.2 30. Updated ”DATA – Data register” on page 284. Added the description of ADDR[7:1] and ADDR[0]. 31. Updated the formula in ”Fractional Baud Rate Generation” on page 304. 32. Updated Figure 23-9 on page 305, the “Fractional baud rate example.” 33. Added Table 23-5 on page 306, the “USART Baud rate.” 34. Updated Figure 24-1 on page 316, the “IRCOM connection to USARTs and associated port pins.” RXDnx and TXDnxc changed to RXDxn and TXDxn respectively. 35.
Atmel AVR XMEGA AU Table Of Contents 1 About the Manual ..................................................................................... 2 1.1 Reading the Manual ..........................................................................................2 1.2 Resources .........................................................................................................2 1.3 Recommended Reading ....................................................................................2 2 Overview ...
Atmel AVR XMEGA AU 5 6 4.12 Device ID and Revision ...................................................................................25 4.13 JTAG Disable ..................................................................................................25 4.14 I/O Memory Protection .....................................................................................25 4.15 Register Description – NVM Controller ............................................................26 4.
Atmel AVR XMEGA AU 7 8 9 6.2 Overview ..........................................................................................................71 6.3 Events ..............................................................................................................72 6.4 Event Routing Network ....................................................................................74 6.5 Event Timing ....................................................................................................
Atmel AVR XMEGA AU 9.1 Features ........................................................................................................113 9.2 Overview ........................................................................................................113 9.3 Reset Sequence ............................................................................................114 9.4 Reset Sources ...............................................................................................115 9.
Atmel AVR XMEGA AU 13.2 Overview ........................................................................................................143 13.3 I/O Pin Use and Configuration .......................................................................144 13.4 Reading the Pin Value ...................................................................................147 13.5 Input Sense Configuration .............................................................................148 13.6 Port Interrupt ......
Atmel AVR XMEGA AU 15.2 Overview ........................................................................................................193 15.3 Block Diagram ...............................................................................................194 15.4 Clock Sources ...............................................................................................194 15.5 Counter Operation .........................................................................................195 15.
Atmel AVR XMEGA AU 19.4 Register Summary .........................................................................................234 19.5 Interrupt Vector Summary .............................................................................234 20 USB – Universal Serial Bus Interface ................................................. 235 20.1 Features ........................................................................................................235 20.2 Overview ..............................
Atmel AVR XMEGA AU 21.13 Register Summary - TWI Slave .....................................................................286 21.14 Interrupt Vector Summary .............................................................................286 22 SPI – Serial Peripheral Interface ......................................................... 287 22.1 Features ........................................................................................................287 22.2 Overview ...............................
Atmel AVR XMEGA AU 25 AES and DES Crypto Engines ............................................................ 320 25.1 Features ........................................................................................................320 25.2 Overview ........................................................................................................320 25.3 DES Instruction ..............................................................................................320 25.4 AES Crypto Module .....
Atmel AVR XMEGA AU 28.4 ADC Channels ...............................................................................................360 28.5 Voltage Reference Selection .........................................................................361 28.6 Conversion Result .........................................................................................361 28.7 Compare Function .........................................................................................363 28.
Atmel AVR XMEGA AU 30.6 Window Mode ................................................................................................400 30.7 Input Hysteresis .............................................................................................400 30.8 Propagation Delay vs. Power Consumption ..................................................400 30.9 Register Description ......................................................................................401 30.10 Register Summary ..........
Atmel AVR XMEGA AU 33.13 Register Description ......................................................................................452 33.14 Register Summary .........................................................................................452 34 Peripheral Module Address Map ........................................................ 453 35 Instruction Set Summary .................................................................... 456 36 Appendix A: EBI Timing Diagrams ...........................
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