Datasheet

92
2586N–AVR–04/11
ATtiny25/45/85
12.3 Register Description
12.3.1 TCCR1 – Timer/Counter1 Control Register
Bit 7 – CTC1 : Clear Timer/Counter on Compare Match
When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle
after a compare match with OCR1C register value. If the control bit is cleared, Timer/Counter1
continues counting and is unaffected by a compare match.
Bit 6 – PWM1A: Pulse Width Modulator A Enable
When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1
and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C
register value.
Bits 5:4 – COM1A[1:0]: Comparator A Output Mode, Bits 1 and 0
The COM1A1 and COM1A0 control bits determine any output pin action following a compare
match with compare register A in Timer/Counter1. Since the output pin action is an alternative
function to an I/O port, the corresponding direction control bit must be set (one) in order to con-
trol an output pin.
In Normal mode, the COM1A1 and COM1A0 control bits determine the output pin actions that
affect pin PB1 (OC1A) as described in Table 12-4. Note that OC1A
is not connected in normal
mode.
In PWM mode, these bits have different functions. Refer to Table 12-1 on page 89 for a detailed
description.
Bits 3:0 - CS1[3:0]: Clock Select Bits 3, 2, 1, and 0
The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.
Bit 7 6 5 4 3 2 1 0
0x30 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 TCCR1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 12-4. Comparator A Mode Select in Normal Mode
COM1A1 COM1A0 Description
0 0 Timer/Counter Comparator A disconnected from output pin OC1A.
0 1 Toggle the OC1A output line.
1 0 Clear the OC1A output line.
1 1 Set the OC1A output line
Table 12-5. Timer/Counter1 Prescale Select
CS13 CS12 CS11 CS10
Asynchronous
Clocking Mode
Synchronous
Clocking Mode
0 0 0 0 T/C1 stopped T/C1 stopped
0001PCK CK
0 0 1 0 PCK/2 CK/2
0 0 1 1 PCK/4 CK/4