Datasheet

70
2586N–AVR–04/11
ATtiny25/45/85
Figure 11-3. Timer/Counter0 Prescaler
The synchronization logic on the input pins (T0) in Figure 11-3 is shown in Figure 11-2 on page
69.
11.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
11-4 shows a block diagram of the counter and its surroundings.
Figure 11-4. Counter Unit Block Diagram
Signal description (internal signals):
count Increment or decrement TCNT0 by 1.
direction Select between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
clk
Tn
Timer/Counter clock, referred to as clk
T0
in the following.
top Signalize that TCNT0 has reached maximum value.
bottom Signalize that TCNT0 has reached minimum value (zero).
PSR10
Clear
clk
T0
T0
clk
I/O
Synchronization
DATA BUS
TCNTn Control Logic
count
TOVn
(Int.Req.)
Clock Select
top
Tn
Edge
Detector
( From Prescaler )
clk
Tn
bottom
direction
clear