Datasheet

28
2586N–AVR–04/11
ATtiny25/45/85
Mode” on page 98). Note that in this mode of operation the 6.4 MHz clock signal is always
divided by four, providing a 1.6 MHz system clock.
Note: 1. The device is shipped with this option selected.
2. This setting will select ATtiny15 Compatibility Mode, where system clock is divided by four,
resulting in a 1.6 MHz clock frequency.
When the calibrated 8 MHz internal oscillator is selected as clock source the start-up times are
determined by the SUT Fuses as shown in Table 6-7 below.
Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to
ensure programming mode can be entered.
2. The device is shipped with this option selected.
In ATtiny15 Compatibility Mode start-up times are determined by SUT fuses as shown in Table
6-8 below.
Note: 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to
ensure programming mode can be entered.
In summary, more information on ATtiny15 Compatibility Mode can be found in sections “Port B
(PB5:PB0)” on page 2, “Internal PLL in ATtiny15 Compatibility Mode” on page 24, “8-bit
Timer/Counter1 in ATtiny15 Mode” on page 98, “Limitations of debugWIRE” on page 144, “Cali-
bration Bytes” on page 154 and in table “Clock Prescaler Select” on page 34.
Table 6-6. Internal Calibrated RC Oscillator Operating Modes
CKSEL[3:0] Nominal Frequency
0010
(1)
8.0 MHz
0011
(2)
6.4 MHz
Table 6-7. Start-up Times for Internal Calibrated RC Oscillator Clock
SUT[1:0]
Start-up Time
from Power-down
Additional Delay from
Reset (V
CC
= 5.0V) Recommended Usage
00 6 CK 14CK
(1)
BOD enabled
01 6 CK 14CK + 4 ms Fast rising power
10
(2)
6 CK 14CK + 64 ms Slowly rising power
11 Reserved
Table 6-8. Start-up Times for Internal Calibrated RC Oscillator Clock (in ATtiny15 Mode)
SUT[1:0]
Start-up Time
from Power-down
Additional Delay from
Reset (V
CC
= 5.0V) Recommended Usage
00 6 CK 14CK + 64 ms
01 6 CK 14CK + 64 ms
10 6 CK 14CK + 4 ms
11 1 CK 14CK
(1)