Datasheet

26
2586N–AVR–04/11
ATtiny25/45/85
mal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time.
The number of WDT Oscillator cycles used for each time-out is shown in Table 6-2.
6.2.1 External Clock
To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-
4. To run the device on an external clock, the CKSEL Fuses must be programmed to “00”.
Figure 6-4. External Clock Drive Configuration
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 6-3.
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page
31 for details.
6.2.2 High Frequency PLL Clock
There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator
for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as
Table 6-2. Number of Watchdog Oscillator Cycles
Typ Time-out Number of Cycles
4 ms 512
64 ms 8K (8,192)
Table 6-3. Start-up Times for the External Clock Selection
SUT[1:0]
Start-up Time from
Power-down
Additional Delay from
Reset Recommended Usage
00 6 CK 14CK BOD enabled
01 6 CK 14CK + 4 ms Fast rising power
10 6 CK 14CK + 64 ms Slowly rising power
11 Reserved
EXTERNAL
CLOCK
SIGNAL
CLKI
GND