Datasheet

156
2586N–AVR–04/11
ATtiny25/45/85
20.5.1 Serial Programming Algorithm
When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK.
When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See
Figure 21-4 and Figure 21-5 for timing details.
To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following
sequence is recommended (see four byte instruction formats in Table 20-12):
1. Power-up sequence: apply power between V
CC
and GND while RESET and SCK are
set to “0”
– In some systems, the programmer can not guarantee that SCK is held low during
power-up. In this case, RESET
must be given a positive pulse after SCK has been
set to '0'. The duration of the pulse must be at least t
RST
plus two CPU clock cycles.
See Table 21-4 on page 170 for minimum pulse width on RESET
pin, t
RST
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of syn-
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET
a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
a time by supplying the 5 LSB of the address and data together with the Load Program
memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program memory
Page is stored by loading the Write Program memory Page instruction with the 6 MSB
of the address. If polling (RDY/BSY)
is not used, the user must wait at least t
WD_FLASH
before issuing the next page. (See Table 20-11.) Accessing the serial programming
interface before the Flash write operation completes can result in incorrect
programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling (RDY/BSY)
is not used,
the user must wait at least t
WD_EEPROM
before issuing the next byte. (See Table 20-11.)
In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 2 LSB of the address and data together with the
Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by
loading the Write EEPROM Memory Page Instruction with the 6 MSB of the address.
When using EEPROM page access only byte locations loaded with the Load EEPROM
Memory Page instruction is altered. The remaining locations remain unchanged. If poll-
ing (RDY/BSY)
is not used, the used must wait at least t
WD_EEPROM
before issuing the
next page (See Table 20-9). In a chip erased device, no 0xFF in the data file(s) need to
be programmed.
6. Any memory location can be verified by using the Read instruction which returns the
content at the selected address at serial output MISO.
7. At the end of the programming session, RESET
can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET
to “1”.
Turn V
CC
power off.