Datasheet

139
2586N–AVR–04/11
ATtiny25/45/85
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a comple te description of this bit, see “ADCL and ADCH – The ADC Data Register”
on page 141.
• Bits 3:0 – MUX[3:0]: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC. In
case of differential input (ADC0 - ADC1 or ADC2 - ADC3), gain selection is also made with these
bits. Selecting ADC2 or ADC0 as both inputs to the differential gain stage enables offset mea-
surements. Selecting the single-ended channel ADC4 enables the temperature sensor. Refer to
Table 17-4 for details. If these bits are changed during a conversion, the change will not go into
effect until this conversion is complete (ADIF in ADCSRA is set).
Note: 1. For offset calibration, only. See “Operation” on page 127.
2. After switching to internal voltage reference the ADC requires a settling time of 1ms before
measurements are stable. Conversions starting before this may not be reliable. The ADC must
be enabled during the settling time.
3. For temperature sensor.
Table 17-4. Input Channel Selections
MUX[3:0]
Single Ended
Input
Positive
Differential Input
Negative
Differential Input Gain
0000 ADC0 (PB5)
N/A
0001 ADC1 (PB2)
0010 ADC2 (PB4)
0011 ADC3 (PB3)
0100
N/A
ADC2 (PB4) ADC2 (PB4) 1x
0101
(1)
ADC2 (PB4) ADC2 (PB4) 20x
0110 ADC2 (PB4) ADC3 (PB3) 1x
0111 ADC2 (PB4) ADC3 (PB3) 20x
1000 ADC0 (PB5) ADC0 (PB5) 1x
1001 ADC0 (PB5) ADC0 (PB5) 20x
1010 ADC0 (PB5) ADC1 (PB2) 1x
1011 ADC0 (PB5) ADC1 (PB2) 20x
1100
(2)
V
BG
N/A
1101 GND
1110 N/A
1111
(3)
ADC4