Datasheet

120
2586N–AVR–04/11
ATtiny25/45/85
15.5.4 USICR – USI Control Register
The USI Control Register includes bits for interrupt enable, setting the wire mode, selecting the
clock and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the start condition detector interrupt. If there is a pending interrupt
and USISIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed
immediately. Refer to the USISIF bit description on page 119 for further details.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the counter overflow interrupt. If there is a pending interrupt and
USIOIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed imme-
diately. Refer to the USIOIF bit description on page 119 for further details.
• Bits 5:4 – USIWM[1:0]: Wire Mode
These bits set the type of wire mode to be used, as shown in Table 15-1 below.
Note: 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively
to avoid confusion between the modes of operation.
Bit 7 6 5 4 3 2 1 0
0x0D USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC USICR
Read/Write R/W R/W R/W R/W R/W R/W W W
Initial Value 0 0 0 0 0 0 0 0
Table 15-1. Relationship between USIWM[1:0] and USI Operation
USIWM1 USIWM0 Description
00
Outputs, clock hold, and start detector disabled.
Port pins operates as normal.
01
Three-wire mode. Uses DO, DI, and USCK pins.
The Data Output (DO) pin overrides the corresponding bit in the PORTB register.
However, the corresponding DDRB bit still controls the data direction. When the port pin is
set as input the pin pull-up is controlled by the PORTB bit.
The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port operation.
When operating as master, clock pulses are software generated by toggling the PORTB
register, while the data direction is set to output. The USITC bit in the USICR Register can
be used for this purpose.
10
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins
(1)
.
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and use open-
collector output drives. The output drivers are enabled by setting the corresponding bit for
SDA and SCL in the DDRB register.
When the output driver is enabled for the SDA pin it will force the line SDA low if the output
of the USI Data Register or the corresponding bit in the PORTB register is zero.
Otherwise, the SDA line will not be driven (i.e., it is released). When the SCL pin output
driver is enabled the SCL line will be forced low if the corresponding bit in the PORTB
register is zero, or by the start detector. Otherwise the SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition and the output is
enabled. Clearing the Start Condition Flag (USISIF) releases the line. The SDA and SCL
pin inputs is not affected by enabling this mode. Pull-ups on the SDA and SCL port pin are
disabled in Two-wire mode.
11
Two-wire mode. Uses SDA and SCL pins.
Same operation as in two-wire mode above, except that the SCL line is also held low
when a counter overflow occurs, and until the Counter Overflow Flag (USIOIF) is cleared.