Datasheet

111
2586N–AVR–04/11
ATtiny25/45/85
15. USI – Universal Serial Interface
15.1 Features
• Two-wire Synchronous Data Transfer (Master or Slave)
• Three-wire Synchronous Data Transfer (Master or Slave)
• Data Received Interrupt
• Wakeup from Idle Mode
• Wake-up from All Sleep Modes In Two-wire Mode
• Two-wire Start Condition Detector with Interrupt Capability
15.2 Overview
The Universal Serial Interface (USI), provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown in Figure 15-1 For actual placement of I/O pins
refer to “Pinout ATtiny25/45/85” on page 2. Device-specific I/O Register and bit locations are
listed in the “Register Descriptions” on page 118.
Figure 15-1. Universal Serial Interface, Block Diagram
The 8-bit USI Data Register (USIDR) contains the incoming and outgoing data. It is directly
accessible via the data bus but a copy of the contents is also placed in the USI Buffer Register
(USIBR) where it can be retrieved later. If reading the USI Data Register directly, the register
must be read as quickly as possible to ensure that no data is lost.
The most significant bit of the USI Data Register is connected to one of two output pins (depend-
ing on the mode configuration, see “USICR – USI Control Register” on page 120). There is a
transparent latch between the output of the USI Data Register and the output pin, which delays
DATA BUS
USIPF
USITC
USICLK USICS0 USICS1
USIOIFUSIOIE
USIDC
USISIF
USIWM0
USIWM1
USISIE Bit7
Two-wire
Clock
Control Unit
DO
(Output only)
DI/SDA
(Input/Open Drain)
USCK/SCL
(Input/Open Drain)
4-bit Counter
USIDR
USISR
DQ
LE
USICR
CLOCK
HOLD
TIM0 COMP
Bit0
[1]
3
0
1
2
3
0
1
2
0
1
2
USIBR