Datasheet

102
2586N–AVR–04/11
ATtiny25/45/85
When OCR1A contains $00 or the top value, as specified in OCR1C register, the output
PB1(OC1A) is held low or high according to the settings of COM1A1/COM1A0. This is shown in
Table 13-2.
In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C
value and the TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is
set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to
the Timer Output Compare flags and interrupts.
The PWM frequency can be derived from the timer/counter clock frequency using the following
equation:
The duty cycle of the PWM waveform can be calculated using the following equation:
...where T
PCK
is the period of the fast peripheral clock (1/25.6 MHz = 39.1 ns).
Resolution indicates how many bits are required to express the value in the OCR1C register. It
can be calculated using the following equation:
Table 13-2. PWM Outputs OCR1A = $00 or OCR1C
COM1A1 COM1A0 OCR1A Output OC1A
01$00L
0 1 OCR1C H
10$00L
1 0 OCR1C H
11$00H
1 1 OCR1C L
Table 13-3. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode
PWM Frequency Clock Selection CS1[3:0] OCR1C RESOLUTION
20 kHz PCK/16 0101 199 7.6
30 kHz PCK/16 0101 132 7.1
40 kHz PCK/8 0100 199 7.6
50 kHz PCK/8 0100 159 7.3
60 kHz PCK/8 0100 132 7.1
70 kHz PCK/4 0011 228 7.8
f
f
TCK1
OCR1C + 1()
----------------------------------- -=
D
OCR1A 1+()T
TCK1
T
PCK
–×
OCR1C 1+()T
TCK1
×
----------------------------------------------------------------------------=
R 2OCR1C 1+()log=