Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 2/4/8K Bytes of In-System Programmable Program Memory Flash • Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 128/256/512 Bytes Internal SR
1. Pin Configurations Figure 1-1.
ATtiny25/45/85 resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in “Alternate Functions of Port B” on page 62. On ATtiny25, the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in ATtiny15 Compatibility Mode for supporting the backward compatibility with ATtiny15. 1.1.4 RESET Reset input.
2. Overview The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1.
ATtiny25/45/85 registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
3. About 3.1 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
ATtiny25/45/85 4. AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.2 Architectural Overview Figure 4-1.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
ATtiny25/45/85 4.4.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 0x3F I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
4.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATtiny25/45/85 Figure 4-3. The X-, Y-, and Z-registers 15 X-register XH XL 7 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.
4.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept.
ATtiny25/45/85 When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 4.8.
ATtiny25/45/85 5. AVR Memories This section describes the different memories in the ATtiny25/45/85. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATtiny25/45/85 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 5.1 In-System Re-programmable Flash Program Memory The ATtiny25/45/85 contains 2/4/8K bytes On-chip In-System Reprogrammable Flash memory for program storage.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of internal data SRAM in the ATtiny25/45/85 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10. Figure 5-2.
ATtiny25/45/85 The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used.
The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATtiny25/45/85 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
5.4 I/O Memory The I/O space definition of the ATtiny25/45/85 is shown in “Register Summary” on page 205. All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
ATtiny25/45/85 5.5.3 EECR – EEPROM Control Register Bit 7 6 5 4 3 2 1 0 0x1C – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0 EECR • Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read as 0 in ATtiny25/45/85. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit.
• Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation.
ATtiny25/45/85 6. System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 35. The clock systems are detailed below. Figure 6-1.
6.1.4 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 6.1.5 Internal PLL for Fast Peripheral Clock Generation - clkPCK The internal PLL in ATtiny25/45/85 generates a clock frequency that is 8x multiplied from a source input. By default, the PLL uses the output of the internal, 8.0 MHz RC oscillator as source.
ATtiny25/45/85 In the ATtiny15 compatibility mode the frequency of the internal RC oscillator is calibrated down to 6.4 MHz and the multiplication factor of the PLL is set to 4x. See Figure 6-3. With these adjustments the clocking system is ATtiny15-compatible and the resulting fast peripheral clock has a frequency of 25.6 MHz (same as in ATtiny15). Figure 6-3. PCK Clocking System in ATtiny15 Compatibility Mode. OSCCAL PLLE PLL 8x 1/2 25.6 MHz PCK 3.2 MHz LOCK DETECTOR 6.4 MHz OSCILLATOR 1/4 1.
mal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 6-2. Table 6-2. 6.2.1 Number of Watchdog Oscillator Cycles Typ Time-out Number of Cycles 4 ms 512 64 ms 8K (8,192) External Clock To drive the device from an external clock source, CLKI should be driven as shown in Figure 64. To run the device on an external clock, the CKSEL Fuses must be programmed to “00”. Figure 6-4.
ATtiny25/45/85 a system clock source, by programming the CKSEL fuses to ‘0001’, it is divided by four like shown in Table 6-4. Table 6-4. High Frequency PLL Clock Operating Modes CKSEL[3:0] Nominal Frequency 0001 16 MHz When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 6-5. Table 6-5. 6.2.3 Start-up Times for the High Frequency PLL Clock SUT[1:0] Start-up Time from Power Down Additional Delay from Power-On Reset (VCC = 5.
Mode” on page 98). Note that in this mode of operation the 6.4 MHz clock signal is always divided by four, providing a 1.6 MHz system clock. Table 6-6. Internal Calibrated RC Oscillator Operating Modes CKSEL[3:0] Note: Nominal Frequency (1) 0010 8.0 MHz 0011(2) 6.4 MHz 1. The device is shipped with this option selected. 2. This setting will select ATtiny15 Compatibility Mode, where system clock is divided by four, resulting in a 1.6 MHz clock frequency.
ATtiny25/45/85 6.2.4 Internal 128 kHz Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25°C. This clock may be select as the system clock by programming the CKSEL Fuses to “0100”. When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-9. Table 6-9.
6.2.6 Crystal Oscillator / Ceramic Resonator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 6-5. Either a quartz crystal or a ceramic resonator may be used. Figure 6-5. Crystal Oscillator Connections C2 C1 XTAL2 XTAL1 GND C1 and C2 should always be equal for both crystals and resonators.
ATtiny25/45/85 Table 6-13.
6.4 Clock Output Buffer The device can output the system clock on the CLKO pin (when not used as XTAL2 pin). To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. Note that the clock will not be output during reset and that the normal operation of the I/O pin will be overridden when the fuse is programmed.
ATtiny25/45/85 6.5.2 CLKPR – Clock Prescale Register Bit 7 6 5 4 3 2 1 0 CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0x26 CLKPR See Bit Description • Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaniosly written to zero.
device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 6-15.
ATtiny25/45/85 7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.
the Analog Comparator can be powered down by setting the ACD bit in “ACSR – Analog Comparator Control and Status Register” on page 124. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.
ATtiny25/45/85 7.2.1 Limitations BOD disable functionality has been implemented in the following devices, only: • ATtiny25, revision E, and newer • ATtiny45, revision D, and newer • ATtiny85, revision C, and newer Revisions are marked on the device package and can be located as follows: • Bottom side of packages 8P3 and 8S2 • Top side of package 20M1 7.
7.4.3 Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. See “Brown-out Detection” on page 43 and “Software BOD Disable” on page 36 for details on how to configure the Brown-out Detector. 7.4.
ATtiny25/45/85 In order to disable BOD during sleep (see Table 7-1 on page 35) the BODS bit must be written to logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR. First, both BODS and BODSE must be set to one. Second, within four clock cycles, BODS must be set to one and BODSE must be set to zero. The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode.
• Bit 2 – PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 1 – PRUSI: Power Reduction USI Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re initialized to ensure proper operation. • Bit 0 – PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC.
ATtiny25/45/85 8. System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic.
8.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in “System and Reset Characteristics” on page 170. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
ATtiny25/45/85 Figure 8-4. External Reset During Operation CC 8.2.3 Brown-out Detection ATtiny25/45/85 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
Figure 8-6. Watchdog Reset During Operation CC CK 8.3 Internal Voltage Reference ATtiny25/45/85 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 8.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in “System and Reset Characteristics” on page 170.
ATtiny25/45/85 “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45 for details. Table 8-1.
8.4.2 Code Example The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATtiny25/45/85 • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
• Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This bit must also be set when changing the prescaler bits. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45.
ATtiny25/45/85 Table 8-3. Watchdog Timer Prescale Select (Continued) WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 1 0 0 1 1024K (1048576) cycles 8.0 s 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 Note: Reserved(1) 1. If selected, one of the valid settings below 0b1010 will be used.
9. Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny25/45/85. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. 9.1 Interrupt Vectors in ATtiny25/45/85 The interrupt vectors of ATtiny25/45/85 are described in Table 9-1below. Table 9-1. Reset and Interrupt Vectors Vector No.
ATtiny25/45/85 A typical and general setup for interrupt vector addresses in ATtiny25/45/85 is shown in the program example below. Assembly Code Example .
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 23.
ATtiny25/45/85 9.3 9.3.1 Register Description MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.
9.3.3 GIFR – General Interrupt Flag Register Bit 7 6 5 4 3 2 1 0x3A – INTF0 PCIF – – – – 0 – Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 GIFR • Bits 7, 4:0 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
ATtiny25/45/85 10. I/O Ports 10.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
10.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O(1) PUD Q D DDxn Q CLR WDx RESET DATA BUS RDx 1 Q Pxn D 0 PORTxn Q CLR RESET WRx WPx RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 10.2.
ATtiny25/45/85 10.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
ATtiny25/45/85 C Code Example unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<
Figure 10-5.
ATtiny25/45/85 Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 10-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
10.3.1 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-3. Table 10-3.
ATtiny25/45/85 • Port B, Bit 4 – XTAL2/CLKO/ADC2/OC1B/PCINT4 • XTAL2: Chip Clock Oscillator pin 2. Used as clock pin for all chip clock sources except internal calibrateble RC Oscillator and external clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC Oscillator or External clock as a Chip clock sources, PB4 serves as an ordinary I/O pin. • CLKO: The devided system clock can be output on the pin PB4.
set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function. • OC1A: Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter1 Compare Match B when configured as an output (DDB1 set). The OC1A pin is also the output pin for the PWM mode timer function. • DO: Three-wire mode Universal Serial Interface Data output.
ATtiny25/45/85 Table 10-4.
10.4 10.4.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x35 MCUCR • Bit 6 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
ATtiny25/45/85 11. 8-bit Timer/Counter0 with PWM 11.1 Features • • • • • • • 11.2 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support.
11.2.1 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin.
ATtiny25/45/85 of the prescaler will have implications for situations where a prescaled clock is used. One example of a prescaling artifact is when the timer/counter is enabled and clocked by the prescaler (6 > CS0[2:0] > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
Figure 11-3. Timer/Counter0 Prescaler clk I/O Clear PSR10 T0 Synchronization clkT0 The synchronization logic on the input pins (T0) in Figure 11-3 is shown in Figure 11-2 on page 69. 11.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 11-4 shows a block diagram of the counter and its surroundings. Figure 11-4. Counter Unit Block Diagram TOVn (Int.Req.
ATtiny25/45/85 Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS0[2:0]). When no clock source is selected (CS0[2:0] = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
ATtiny25/45/85 Figure 11-6. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCnx DATA BUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x[1:0] bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
sequence, while the Waveform Generation mode bits do. The COM0x[1:0] bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For nonPWM modes the COM0x[1:0] bits control whether the output should be set, cleared, or toggled at a Compare Match (See “Compare Match Output Unit” on page 72.). For detailed timing information refer to Figure 11-10, Figure 11-11, Figure 11-12 and Figure 1113 in “Timer/Counter Timing Diagrams” on page 78. 11.7.
ATtiny25/45/85 ning with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur.
Figure 11-8. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCn (COMnx[1:0] = 2) OCn (COMnx[1:0] = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
ATtiny25/45/85 11.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM0[2:0] = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM0[2:0] = 1, and OCR0A when WGM0[2:0] = 5.
not available for the OC0B pin (See Table 11-4 on page 81). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0 when the counter decrements.
ATtiny25/45/85 Figure 11-11. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 11-12 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 11-12.
11.9 11.9.1 Register Description GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x2C TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 Read/Write R/W R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization Mode. In this mode, the value written to PSR0 is kept, hence keeping the Prescaler Reset signal asserted.
ATtiny25/45/85 Table 11-3 shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to fast PWM mode. Table 11-3. Compare Output Mode, Fast PWM Mode(1) COM0A1 COM0B1 COM0A0 COM0B0 0 0 Normal port operation, OC0A/OC0B disconnected. 0 1 Reserved 1 0 Clear OC0A/OC0B on Compare Match, set OC0A/OC0B at BOTTOM (non-inverting mode) 1 1 Set OC0A/OC0B on Compare Match, clear OC0A/OC0B at BOTTOM (inverting mode) Note: Description 1.
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 73). Table 11-5.
ATtiny25/45/85 A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the “TCCR0A – Timer/Counter Control Register A” on page 80.
11.9.6 OCR0B – Output Compare Register B Bit 7 6 5 0x28 4 3 2 1 0 OCR0B[7:0] OCR0B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin. 11.9.
ATtiny25/45/85 the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. • Bit 3 – OCF0B: Output Compare Flag 0 B The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag.
12. 8-bit Timer/Counter1 The Timer/Counter1 is a general purpose 8-bit Timer/Counter module that has a separate prescaling selection from the separate prescaler. 12.1 Timer/Counter1 Prescaler Figure 12-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchronous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base.
ATtiny25/45/85 Timer/Counter1 and the output compare registers serve as dual stand-alone PWMs with nonoverlapping non-inverted and inverted outputs. Refer to page 89 for a detailed description on this function. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Figure 12-2. Timer/Counter 1 Synchronization Register Block Diagram.
Figure 12-3. Timer/Counter1 Block Diagram T/C1 OVER- T/C1 COMPARE T/C1 COMPARE FLOW IRQ MATCH A IRQ MATCH B IRQ OC1A (PB1) OC1B (PB4) OC1A (PB0) DEAD TIME GENERATOR TOV0 PSR1 FOC1B FOC1A COM1B0 PWM1B GLOBAL T/C CONTROL REGISTER (GTCCR) COM1B1 CS10 CS12 CS11 CS13 COM1A0 COM1A1 CTC1 TOV1 T/C CONTROL REGISTER 1 (TCCR1) PWM1A OCF1B TOV1 OCF1A OCF1A TIMER INT. FLAG REGISTER (TIFR) OCF1B TOIE1 TOIE0 OCIE1A OCIE1B DEAD TIME GENERATOR TIMER INT.
ATtiny25/45/85 values to obtain PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution. 12.2.1 Timer/Counter1 Initialization for Asynchronous Mode To set Timer/Counter1 in asynchronous mode first enable PLL and then wait 100 µs for PLL to stabilize. Next, poll the PLOCK bit until it is set and then set the PCKE bit. 12.2.
Figure 12-5. Effects of Unsynchronized OCR Latching Compare Value changes Counter Value Compare Value PWM Output OC1x Synchronized OC1x Latch Compare Value changes Counter Value Compare Value PWM Output OC1x Glitch Unsynchronized OC1x Latch During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always will read out of OCR1A or OCR1B.
ATtiny25/45/85 R = log 2(OCR1C + 1) Table 12-3. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode PWM Frequency Clock Selection CS1[3:0] OCR1C RESOLUTION 20 kHz PCK/16 0101 199 7.6 30 kHz PCK/16 0101 132 7.1 40 kHz PCK/8 0100 199 7.6 50 kHz PCK/8 0100 159 7.3 60 kHz PCK/8 0100 132 7.1 70 kHz PCK/4 0011 228 7.8 80 kHz PCK/4 0011 199 7.6 90 kHz PCK/4 0011 177 7.5 100 kHz PCK/4 0011 159 7.3 110 kHz PCK/4 0011 144 7.
12.3 12.3.1 Register Description TCCR1 – Timer/Counter1 Control Register Bit 7 6 5 4 3 2 1 0 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0x30 TCCR1 • Bit 7 – CTC1 : Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.
ATtiny25/45/85 Table 12-5.
In PWM mode, these bits have different functions. Refer to Table 12-1 on page 89 for a detailed description. • Bit 3 – FOC1B: Force Output Compare Match 1B Writing a logical one to this bit forces a change in the compare match output pin PB3 (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the timer value.
ATtiny25/45/85 12.3.5 OCR1B – Timer/Counter1 Output Compare RegisterB Bit 7 6 5 4 3 2 1 0 0x2B MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 OCR1B The output compare register B is an 8-bit read/write register. The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts to the OCR1B value.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero. 12.3.
ATtiny25/45/85 12.3.9 PLLCSR – PLL Control and Status Register Bit 7 6 5 4 3 2 1 0 0x27 LSM - - - - PCKE PLLE PLOCK Read/Write R/W R R R R R/W R/W R Initial value 0 0 0 0 0 0 0/1 0 PLLCSR • Bit 7 – LSM: Low Speed Mode The high speed mode is enabled as default and the fast peripheral clock is 64 MHz, but the low speed mode can be set by writing the LSM bit to one. Then the fast peripheral clock is scaled down to 32 MHz.
13. 8-bit Timer/Counter1 in ATtiny15 Mode The ATtiny15 compatibility mode is selected by writing the code “0011” to the CKSEL fuses (if any other code is written, the Timer/Counter1 is working in normal mode). When selected the ATtiny15 compatibility mode provides an ATtiny15 backward compatible prescaler and Timer/Counter. Furthermore, the clocking system has same clock frequencies as in ATtiny15. 13.1 Timer/Counter1 Prescaler Figure 13-1 shows an ATtiny15 compatible prescaler.
ATtiny25/45/85 101 for a detailed description on this function. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions. Figure 13-2. Timer/Counter 1 Synchronization Register Block Diagram.
Figure 13-3. Timer/Counter1 Block Diagram PSR1 GLOBAL T/C CONTROL REGISTER 2 (GTCCR) FOC1A CS10 CS12 CS11 CS13 COM1A1 COM1A0 T/C CONTROL REGISTER 1 (TCCR1) CTC1 PWM1A TOV1 TOV0 OCF1A TIMER INT. FLAG REGISTER (TIFR) OCF1A TIMER INT.
ATtiny25/45/85 13.2.1 Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register A OCR1A form an 8-bit, free-running and glitch-free PWM generator with output on the PB1(OC1A). When the counter value match the content of OCR1A, the OC1A and output is set or cleared according to the COM1A1/COM1A0 bits in the Timer/Counter1 Control Register A - TCCR1, as shown in Table 13-1.
When OCR1A contains $00 or the top value, as specified in OCR1C register, the output PB1(OC1A) is held low or high according to the settings of COM1A1/COM1A0. This is shown in Table 13-2. Table 13-2. PWM Outputs OCR1A = $00 or OCR1C COM1A1 COM1A0 OCR1A Output OC1A 0 1 $00 L 0 1 OCR1C H 1 0 $00 L 1 0 OCR1C H 1 1 $00 H 1 1 OCR1C L In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C value and the TCNT1 is reset to $00.
ATtiny25/45/85 Table 13-3. 13.3 13.3.1 Timer/Counter1 Clock Prescale Select in the Asynchronous Mode (Continued) PWM Frequency Clock Selection CS1[3:0] OCR1C RESOLUTION 80 kHz PCK/4 0011 199 7.6 90 kHz PCK/4 0011 177 7.5 100 kHz PCK/4 0011 159 7.3 110 kHz PCK/4 0011 144 7.2 120 kHz PCK/4 0011 132 7.1 130 kHz PCK/2 0010 245 7.9 140 kHz PCK/2 0010 228 7.8 150 kHz PCK/2 0010 212 7.7 160 kHz PCK/2 0010 199 7.6 170 kHz PCK/2 0010 187 7.
• Bits 5:4 – COM1A[1:0]: Comparator A Output Mode, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an I/O port, the corresponding direction control bit must be set (one) in order to control an output pin. Table 13-4.
ATtiny25/45/85 13.3.2 GTCCR – General Timer/Counter1 Control Register Bit 7 6 5 4 3 2 1 0 0x2C TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 Read/Write R/W R/W R/W R/W W W R/W R/W Initial value 0 0 0 0 0 0 0 0 GTCCR • Bit 2 – FOC1A: Force Output Compare Match 1A Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0.
13.3.5 OCR1C – Timer/Counter1 Output Compare Register C Bit 7 6 5 4 3 2 1 0 0x2D MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 1 1 1 1 1 1 1 1 OCR1C The Output Compare Register B - OCR1B from ATtiny15 is replaced with the output compare register C - OCR1C that is an 8-bit read/write register. This register has the same function as the Output Compare Register B in ATtiny15.
ATtiny25/45/85 • Bit 6 – OCF1A: Output Compare Flag 1A The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchronization clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A compare match interrupt is executed.
14. Dead Time Generator The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be connected to Timer/Counter1 and it is used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary output pairs (OC1A-OC1A and OC1B-OC1B).
ATtiny25/45/85 The length of the counting period is user adjustable by selecting the dead time prescaler setting in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM output and its’ complementary output separately. Thus the rising edge of OC1x and OC1x can have different dead time periods.
14.1.2 DT1A – Timer/Counter1 Dead Time A Bit 7 6 5 4 3 2 1 0 DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0x25 DT1A The dead time value register A is an 8-bit read/write register. The dead time delay of is adjusted by the dead time value register, DT1A. The register consists of two fields, DT1AH[3:0] and DT1AL[3:0], one for each complementary output.
ATtiny25/45/85 15. USI – Universal Serial Interface 15.1 Features • • • • • • 15.2 Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wakeup from Idle Mode Wake-up from All Sleep Modes In Two-wire Mode Two-wire Start Condition Detector with Interrupt Capability Overview The Universal Serial Interface (USI), provides the basic hardware resources needed for serial communication.
the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. The 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same clock source.
ATtiny25/45/85 Figure 15-3. Three-Wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The three-wire mode timing is shown in Figure 15-3 At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
sbrs r16, USIOIF rjmp SPITransfer_loop in r16,USIDR ret The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRB. The value stored in register r16 prior to the function is called is transferred to the slave device, and when the transfer is completed the data received from the slave is stored back into the register r16.
ATtiny25/45/85 ... SlaveSPITransfer: out USIDR,r16 ldi r16,(1<
Figure 15-4 shows two USI units operating in two-wire mode, one as master and one as slave. It is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used. The main differences between the master and slave operation at this level is the serial clock generation which is always done by the master. Only the slave uses the clock control unit.
ATtiny25/45/85 enables its output. If the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line) The slave can hold the SCL line low after the acknowledge (E). 6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is given by the master (F), or a new start condition is given. If the slave is not able to receive more data it does not acknowledge the data byte it has last received.
15.4.3 12-Bit Timer/Counter Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter. 15.4.4 Edge Triggered External Interrupt By setting the counter to maximum value (F) it can function as an additional external interrupt. The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature is selected by the USICS1 bit. 15.4.
ATtiny25/45/85 15.5.3 USISR – USI Status Register Bit 7 6 5 4 3 2 1 0 USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x0E USISR The Status Register contains interrupt flags, line status flags and the counter value. • Bit 7 – USISIF: Start Condition Interrupt Flag When two-wire mode is selected, the USISIF Flag is set (to one) when a start condition has been detected.
15.5.4 USICR – USI Control Register Bit 7 6 5 4 3 2 1 0 USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC Read/Write R/W R/W R/W R/W R/W R/W W W Initial Value 0 0 0 0 0 0 0 0 0x0D USICR The USI Control Register includes bits for interrupt enable, setting the wire mode, selecting the clock and clock strobe. • Bit 7 – USISIE: Start Condition Interrupt Enable Setting this bit to one enables the start condition detector interrupt.
ATtiny25/45/85 Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and USI Data Register can therefore be clocked externally and data input sampled, even when outputs are disabled. • Bits 3:2 – USICS[1:0]: Clock Source Select These bits set the clock source for the USI Data Register and counter.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. The bit will read as zero.
ATtiny25/45/85 16. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle.
16.2 16.2.1 Register Description ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 0x03 BIN ACME IPR – – ADTS2 ADTS1 ADTS0 Read/Write R/W R/W R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator.
ATtiny25/45/85 • Bits 1:0 – ACIS[1:0]: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 16-2. Table 16-2. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge.
17. Analog to Digital Converter 17.1 Features • • • • • • • • • • • • • • • • • 17.2 10-bit Resolution 1 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 65 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution Four Multiplexed Single Ended Input Channels Two differential input channels with selectable gain Temperature sensor input channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.1V / 2.
ATtiny25/45/85 Figure 17-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] REFS[2:0] ADC[9:0] ADPS1 TRIGGER SELECT MUX DECODER VCC PRESCALER INTERNAL 1.1V/2.56V REFERENCE GAIN SELECTION CHANNEL SELECTION START AREF CONVERSION LOGIC TEMPERATURE SENSOR SAMPLE & HOLD COMPARATOR 10-BIT DAC ADC4 ADC3 ADC2 0 ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADPS2 ADIF ADSC ADEN ADLAR MUX1 MUX0 MUX2 BIN IPR 15 ADC CTRL.
If ADC0 or ADC2 is selected as both the positive and negative input to the differential gain amplifier (ADC0-ADC0 or ADC2-ADC2), the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the conversion. This figure can be subtracted from subsequent conversions with the same gain setting to reduce offset error to below 1 LSW.
ATtiny25/45/85 Figure 17-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. 17.5 Prescaling and Conversion Timing Figure 17-3.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry, as shown in Figure 17-4 below. Figure 17-4.
ATtiny25/45/85 Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 8 9 Next Conversion 10 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Prescaler Reset Prescaler Reset Conversion Complete MUX and REFS Update In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. Figure 17-7.
17.6 Changing Channel or Reference Selection The MUX[3:0] and REFS[2:0] bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and voltage reference selection only takes place at a safe point during the conversion. The channel and voltage reference selection is continuously updated until a conversion is started.
ATtiny25/45/85 Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: • Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. • Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted.
17.9 Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: • Keep analog signal paths as short as possible. • Make sure analog tracks run over the analog ground plane. • Keep analog tracks well away from high-speed switching digital tracks.
ATtiny25/45/85 • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 17-10. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 17-12. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.
ATtiny25/45/85 0x3FF represents the selected voltage reference minus one LSB. The result is presented in onesided form, from 0x3FF to 0x000. 17.11.
assuming calibration at room temperature. Better accuracies are achieved by using two temperature points for calibration. Table 17-2. Temperature vs. Sensor Output Voltage (Typical Case) -40°C +25°C +85°C 230 LSB 300 LSB 370 LSB Temperature ADC The values described in Table 17-2 are typical values. However, due to process variation the temperature sensor output voltage varies from one chip to another.
ATtiny25/45/85 • Bit 5 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a comple te description of this bit, see “ADCL and ADCH – The ADC Data Register” on page 141.
17.13.2 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x06 ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATtiny25/45/85 Table 17-5. 17.13.3 17.13.3.1 ADPS2 ADPS1 ADPS0 Division Factor 1 0 1 32 1 1 0 64 1 1 1 128 ADCL and ADCH – The ADC Data Register ADLAR = 0 Bit 15 14 13 12 11 10 9 8 0x05 – – – – – – ADC9 ADC8 ADCH 0x04 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL Read/Write Initial Value 17.13.3.
are supported and the voltage on the positive input must always be larger than the voltage on the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode two-sided conversions are supported and the result is represented in the two’s complement form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits + 1 sign bit.
ATtiny25/45/85 18. debugWIRE On-chip Debug System 18.1 Features • • • • • • • • • • 18.
When designing a system where debugWIRE will be used, the following must be observed: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the pull-up resistor is optional. • Connecting the RESET pin directly to VCC will not work. • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 18.4 Software Break Points debugWIRE supports Program memory Break Points by the AVR Break instruction.
ATtiny25/45/85 19. Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The SPM instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse (to “0”). The Program memory is updated in a page by page fashion.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 19.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. Note: 19.4 The CPU is halted during the Page Write operation.
ATtiny25/45/85 19.5 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 19.
To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 Refer to Table 20-4 on page 152 for detailed description and mapping of the Fuse High Byte. To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and repeat the previous procedure.
ATtiny25/45/85 19.7 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
• Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost. • Bit 3 – RFLB: Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “EEPROM Write Prevents Writing to SPMCSR” on page 147 for details.
ATtiny25/45/85 20. Memory Programming This section describes the different methods for Programming the ATtiny25/45/85 memories. 20.1 Program And Data Memory Lock Bits ATtiny25/45/85 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional security listed in Table 20-2. Lock bits can be erased to “1” with the Chip Erase command, only.
20.2 Fuse Bytes ATtiny25/45/85 has three fuse bytes, as described in Table 20-3, Table 20-4, and Table 20-5. Note that fuses are read as logical zero, “0”, when programmed. Table 20-3. Fuse Extended Byte Fuse High Byte SELFPRGEN Notes: (1) Bit No Description Default Value 7 - 1 (unprogrammed) 6 - 1 (unprogrammed) 5 - 1 (unprogrammed) 4 - 1 (unprogrammed) 3 - 1 (unprogrammed) 2 - 1 (unprogrammed) 1 - 1 (unprogrammed) 0 Self-programming enabled 1 (unprogrammed) 1.
ATtiny25/45/85 Table 20-5.
20.3.1 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and high-voltage programming mode, even when the device is locked. Signature bytes can also be read by the device firmware. See section “Reading Lock, Fuse and Signature Data from Software” on page 147. The three signature bytes reside in a separate address space called the device signature imprint table.
ATtiny25/45/85 20.5 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). See below. Figure 20-1. Serial Programming and Verify(1) +1.8 - 5.5V VCC MOSI MISO SCK RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the CLKI pin.
20.5.1 Serial Programming Algorithm When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK. When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See Figure 21-4 and Figure 21-5 for timing details. To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 20-12): 1.
ATtiny25/45/85 20.5.2 Serial Programming Instruction set Table 20-11. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 9.0 ms tWD_FUSE 4.5 ms Table 20-12 on page 157 and Figure 20-2 on page 158 describes the Instruction set. Table 20-12.
Notes: 1. Not all instructions are applicable for all parts. 2. a = address 3. Bits are programmed ‘0’, unprogrammed ‘1’. 4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) . 5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See htt://www.atmel.
ATtiny25/45/85 20.6 High-voltage Serial Programming This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and Fuse bits in the ATtiny25/45/85. Figure 20-3. High-voltage Serial Programming +11.5 - 12.5V SCI +4.5 - 5.5V PB5 (RESET) VCC PB3 PB2 SDO PB1 SII PB0 SDI GND Table 20-13.
20.7.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device in High-voltage Serial Programming mode: 1. Set Prog_enable pins listed in Table 20-14 to “000”, RESET pin and VCC to 0V. 2. Apply 4.5 - 5.5V between VCC and GND. Ensure that VCC reaches at least 1.8V within the next 20 µs. 3. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET. 4.
ATtiny25/45/85 20.7.3 Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the Program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. Note: 1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. 1. Load command “Chip Erase” (see Table 20-16). 2. Wait after Instr.
Figure 20-5. High-voltage Serial Programming Waveforms SDI PB0 MSB LSB SII PB1 MSB LSB SDO PB2 SCI PB3 20.7.5 MSB 0 LSB 1 2 3 4 5 6 7 8 9 10 Programming the EEPROM The EEPROM is organized in pages, see Table 21-11 on page 175. When programming the EEPROM, the data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM Data memory is as follows (refer to Table 20-16): 1. Load Command “Write EEPROM”. 2.
ATtiny25/45/85 Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 Instruction Format Instruction Chip Erase Load “Write Flash” Command Load Flash Page Buffer Instr.1/5 Instr.2/6 Instr.3 SDI 0_1000_0000_00 0_0000_0000_00 0_0000_0000_00 SII 0_0100_1100_00 0_0110_0100_00 0_0110_1100_00 SDO x_xxxx_xxxx_xx x_xxxx_xxxx_xx x_xxxx_xxxx_xx SDI 0_0001_0000_00 SII 0_0100_1100_00 Enter Flash Programming code.
Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued) Instruction Format Instruction Instr.1/5 Instr.2/6 Instr.3 Instr.
ATtiny25/45/85 Notes: 1. a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bits, q = data out low bits, x = don’t care, 1 = Lock Bit1, 2 = Lock Bit2, 3 = CKSEL0 Fuse, 4 = CKSEL1 Fuse, 5 = CKSEL2 Fuse, 6 = CKSEL3 Fuse, 7 = SUT0 Fuse, 8 = SUT1 Fuse, 9 = CKOUT Fuse, A = CKDIV8 Fuse, B = BODLEVEL0 Fuse, C = BODLEVEL1 Fuse, D = BODLEVEL2 Fuse, E = EESAVE Fuse, F = WDTON Fuse, G = SPIEN Fuse, H = DWEN Fuse, I = RSTDISBL Fuse, J = SELFPRGEN Fuse 2.
21. Electrical Characteristics 21.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATtiny25/45/85 Table 21-1. DC Characteristics. TA = -40°C to +85°C (Continued) Symbol Parameter Condition RRST Reset Pull-up Resistor VCC = 5.5V, input low Rpu I/O Pin Pull-up Resistor VCC = 5.5V, input low Power Supply Current (7) ICC Power-down mode (8) Notes: Min. Typ.(1) Max. Units 30 60 kΩ 20 50 kΩ Active 1 MHz, VCC = 2V 0.3 0.55 mA Active 4 MHz, VCC = 3V 1.5 2.5 mA Active 8 MHz, VCC = 5V 5 8 mA Idle 1 MHz, VCC = 2V 0.1 0.2 mA Idle 4 MHz, VCC = 3V 0.35 0.
21.3 Speed Figure 21-1. Maximum Frequency vs. VCC 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V 5.5V Figure 21-2. Maximum Frequency vs. VCC 20 MHz 10 MHz Safe Operating Area 2.7V 168 4.5V 5.
ATtiny25/45/85 21.4 Clock Characteristics 21.4.1 Calibrated Internal RC Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Please note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in Figure 22-40 on page 198 and Figure 2241 on page 198. Table 21-2.
21.5 System and Reset Characteristics Table 21-4. Reset, Brown-out and Internal Voltage Characteristics Parameter Condition Min(1) VRST RESET Pin Threshold Voltage VCC = 3V 0.2 VCC tRST Minimum pulse width on RESET Pin VCC = 3V Symbol VHYST Typ(1) Max(1) Units 0.9 VCC V 2.5 µs Brown-out Detector Hysteresis 50 mV tBOD Min Pulse Width on Brown-out Reset 2 µs VBG Bandgap reference voltage VCC = 5.
ATtiny25/45/85 21.5.2 Enhanced Power-On Reset This implementation of power-on reset exists in newer versions of ATtiny25/45/85. The table below describes the characteristics of this power-on reset and it is valid for the following devices, only: • ATtiny25, revision E, and newer • ATtiny45, revision G, and newer • ATtiny85, revision C, and newer Table 21-6. Symbol Characteristics of Enhanced Power-On Reset. TA = -40°C to +85°C Parameter Release threshold of power-on reset VPOR Typ(1) Max(1) Units 1.
21.7 ADC Characteristics Table 21-8. Symbol ADC Characteristics, Single Ended Channels. TA = -40°C to +85°C Parameter Condition Min Typ Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset errors) VINT VREF = 4V, VCC = 4V, ADC clock = 1 MHz 3 LSB VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 1.5 LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 2.
ATtiny25/45/85 Table 21-9. Symbol ADC Characteristics, Differential Channels (Unipolar Mode). TA = -40°C to +85°C Parameter Condition Min Typ Max Units Gain = 1x 10 Bits Gain = 20x 10 Bits Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 10.0 LSB Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 20.
Table 21-10. ADC Characteristics, Differential Channels (Bipolar Mode). TA = -40°C to +85°C Symbol Parameter Condition Min Typ Max Units Gain = 1x 10 Bits Gain = 20x 10 Bits Resolution Absolute accuracy (Including INL, DNL, and Quantization, Gain and Offset Errors) Integral Non-Linearity (INL) (Accuracy after Offset and Gain Calibration) Gain = 1x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 8.0 LSB Gain = 20x VREF = 4V, VCC = 5V ADC clock = 50 - 200 kHz 8.
ATtiny25/45/85 21.8 Serial Programming Characteristics Figure 21-4. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Figure 21-5. Serial Programming Timing MOSI tSHOX tOVSH SCK tSLSH tSHSL MISO tSLIV Table 21-11. Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V (Unless Otherwise Noted) Symbol Parameter 1/tCLCL Oscillator Frequency (VCC = 1.8 - 5.5V) tCLCL Oscillator Period (VCC = 1.
21.9 High-voltage Serial Programming Characteristics Figure 21-6. High-voltage Serial Programming Timing SDI (PB0), SII (PB1) tIVSH SCI (PB3) tSLSH tSHIX tSHSL SDO (PB2) tSHOV Table 21-12. High-voltage Serial Programming Characteristics TA = 25°C ± 10%, VCC = 5.
ATtiny25/45/85 22. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled.
Figure 22-2. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 14 5.5 V 12 5.0 V ICC (mA) 10 4.5 V 8 4.0V 6 3.3V 4 2.7V 2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 22-3. Active Supply Current vs. VCC (Internal RC oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs.
ATtiny25/45/85 Figure 22-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 1,6 25 ˚C 85 ˚C -40 ˚C 1,4 ICC (mA) 1,2 1 0,8 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) ACTIVE SUPPLY CURRENT vs.
22.2 Idle Supply Current Figure 22-6. Idle Supply Current vs. low Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 0,25 5.5 V 5.0 V 0,2 4.5 V ICC (mA) 4.0 V 0,15 3.3 V 2.7 V 0,1 1.8 V 0,05 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 22-7. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 4 5.5 V 3 5.0 V 2,5 4.5 V ICC (mA) 3,5 2 4.0V 1,5 3.3V 1 2.7V 0,5 1.
ATtiny25/45/85 Figure 22-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)I IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 1,8 85 ˚C 1,6 25 ˚C 1,4 -40 ˚C ICC (mA) 1,2 1 0,8 0,6 0,4 0,2 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-9. Idle Supply Current vs. VCC (Internal RC Oscilllator, 1 MHz) IDLE SUPPLY CURRENT vs.
Figure 22-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 128 kHz 0,1 0,09 -40 ˚C 25 ˚C 0,08 85 ˚C ICC (mA) 0,07 0,06 0,05 0,04 0,03 0,02 0,01 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 22.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode.
ATtiny25/45/85 It is possible to calculate the typical current consumption based on the numbers from Table 22-2 for other VCC and frequency settings that listed in Table 22-1. 22.3.1 Example Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled at VCC = 2.0V and f = 1 MHz. From Table 22-2 on page 182, third column, we see that we need to add 10% for the USI, 25% for the ADC, and 10% for the TIMER0 module.
Figure 22-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 14 12 10 ICC (uA) -40 ˚C 8 25 ˚C 85 ˚C 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 22.5 Pin Pull-up Figure 22-13. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 1.
ATtiny25/45/85 Figure 22-14. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 80 70 60 IOP (uA) 50 40 30 20 25 ˚C 85 ˚C 10 -40 ˚C 0 0 0,5 1 1,5 2 2,5 3 VOP (V) Figure 22-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs.
Figure 22-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 1.8V 40 35 IRESET(uA) 30 25 20 15 10 25 ˚C -40 ˚C 85 ˚C 5 0 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VRESET (V) Figure 22-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC =2.
ATtiny25/45/85 Figure 22-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 5V 120 100 IRESET(uA) 80 60 40 25 ˚C -40 ˚C 85 ˚C 20 0 0 1 2 3 4 5 6 VRESET(V) 22.6 Pin Driver Strength Figure 22-19. I/O Pin Output Voltage vs. Sink Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs.
Figure 22-20. I/O Pin Output Voltage vs. Sink Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 0,6 85 0,5 25 VOL (V) 0,4 -40 0,3 0,2 0,1 0 0 5 10 15 20 25 IOL (mA) Figure 22-21. I/O Pin Output Voltage vs. Source Current (VCC = 3V) I/O PIN OUTPUT VOLTAGE vs.
ATtiny25/45/85 Figure 22-22. I/O Pin Output Voltage vs. Source Current (VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5,1 5 VOH (V) 4,9 4,8 4,7 4,6 -40 25 4,5 85 4,4 0 5 10 15 20 25 IOH (mA) Figure 22-23. Reset Pin Output Voltage vs. Sink Current (VCC = 3V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 3V 1.5 85 °C VOL (V) 1 0 °C -45 °C 0.5 0 0 0.5 1 1.5 2 2.
Figure 22-24. Reset Pin Output Voltage vs. Sink Current (VCC = 5V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT VCC = 5V 1 0.8 VOL (V) 0.6 85 °C 0.4 0 °C -45 °C 0.2 0 0 0.5 1 1.5 2 2.5 3 IOL (mA) Figure 22-25. Reset Pin Output Voltage vs. Source Current (VCC = 3V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 3V 3.5 3 VOH (V) 2.5 2 1.5 -45 °C 25 °C 85 °C 1 0.5 0 0 0.5 1 1.
ATtiny25/45/85 Figure 22-26. Reset Pin Output Voltage vs. Source Current (VCC = 5V) RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT VCC = 5V 5 4.5 VOH (V) 4 3.5 3 -45 °C 25 °C 85 °C 2.5 0 0.5 1 1.5 2 IOH (mA) 22.7 Pin Threshold and Hysteresis Figure 22-27. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’) I/O PIN INPUT THRESHOLD VOLTAGE vs.
Figure 22-28. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 3 85 ˚C 25 ˚C 2,5 Threshold (V) -40 ˚C 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-29. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs.
ATtiny25/45/85 Figure 22-30. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 85 °C 2,5 25 °C -40 °C Threshold (V) 2 1,5 1 0,5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-31. Reset Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’) RESET INPUT THRESHOLD VOLTAGE vs.
Figure 22-32. Reset Pin Input Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs. VCC 0,5 0,45 0,4 Input Hysteresis (V) 0,35 0,3 0,25 0,2 0,15 0,1 -40 °C 25 °C 0,05 85 °C 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) 22.8 BOD Threshold Figure 22-33. BOD Threshold vs. Temperature (BOD Level is 4.3V) BOD THRESHOLDS vs.
ATtiny25/45/85 Figure 22-34. BOD Threshold vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE 2,8 Rising VCC 2,78 Threshold (V) 2,76 2,74 2,72 Falling VCC 2,7 2,68 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Figure 22-35. BOD Threshold vs. Temperature (BOD Level is 1.8V) BOD THRESHOLDS vs.
Figure 22-36. Bandgap Voltage vs. Supply Voltage BANDGAP VOLTAGE vs. VCC 1,2 1,18 1,16 Bandgap Voltage (V) 1,14 1,12 1,1 85 °C 25 °C 1,08 1,06 1,04 -40 °C 1,02 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 Vcc (V) Figure 22-37. Bandgap Voltage vs. Temperature BANDGAP VOLTAGE vs. Temperature 1,2 1,18 1,16 Bandgap Voltage (V) 1,14 1.
ATtiny25/45/85 22.9 Internal Oscillator Speed Figure 22-38. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 0,128 0,126 FRC (MHz) 0,124 -40 ˚C 0,122 25 ˚C 0,12 0,118 0,116 0,114 85 ˚C 0,112 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-39. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 0,12 0,118 FRC (MHz) 0,116 0,114 1.8 V 0,112 2.7 V 3.3 V 0,11 4.0 V 5.
Figure 22-40. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. VCC 8,2 85 ˚C 8,1 FRC (MHz) 8 25 ˚C 7,9 7,8 -40 ˚C 7,7 7,6 7,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-41. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8,15 3.0 V 8,1 8,05 5.
ATtiny25/45/85 Figure 22-42. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 18 85 ˚C 25 ˚C 16 14 -40 ˚C FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) Figure 22-43. Calibrated 1.6 MHz RC Oscillator Frequency vs. VCC CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs.
Figure 22-44. Calibrated 1.6 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 1.6MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1,64 3.0 V 1,62 5.0 V FRC (MHz) 1,6 1,58 1,56 1,54 1,52 1,5 -60 -40 -20 0 20 40 60 80 100 Temperature Figure 22-45. Calibrated 1.6 MHz RC Oscillator Frequency vs. OSCCAL Value CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs.
ATtiny25/45/85 22.10 Current Consumption of Peripheral Units Figure 22-46. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 30 85 °C 25 25 °C -40 °C ICC (uA) 20 15 10 5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-47. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs.
Figure 22-48. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 50 45 85 °C 40 25 °C -40 °C ICC (uA) 35 30 25 20 15 10 5 0 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Figure 22-49. Programming Current vs. VCC PROGRAMMING CURRENT vs.
ATtiny25/45/85 22.11 Current Consumption in Reset and Reset Pulsewidth Figure 22-50. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP ICC (mA) 0,16 0,14 5.5 V 0,12 5.0 V 4.5 V 0,1 4.0 V 0,08 3.3 V 0,06 2.7 V 0,04 1.8 V 0,02 0 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) Figure 22-51. Reset Supply Current vs.
Figure 22-52. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs.
ATtiny25/45/85 23.
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them.
ATtiny25/45/85 24.
Mnemonics Operands Description Operation Flags #Clocks ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..
ATtiny25/45/85 25. Ordering Information 25.
25.2 ATtiny45 Speed (MHz) (1) 10 20 Notes: Supply Voltage (V) 1.8 – 5.5 2.7 – 5.5 Temperature Range Package (2) Ordering Code (3) 8P3 ATtiny45V-10PU 8S2 ATtiny45V-10SU ATtiny45V-10SUR ATtiny45V-10SH 8X ATtiny45V-10XU ATtiny45V-10XUR 20M1 ATtiny45V-10MU ATtiny45V-10MUR 8P3 ATtiny45-20PU 8S2 ATtiny45-20SU ATtiny45-20SUR ATtiny45-20SH 8X ATtiny45-20XU ATtiny45-20XUR 20M1 ATtiny45-20MU ATtiny45-20MUR Industrial (-40°C to +85°C) (4) Industrial (-40°C to +85°C) (4) 1. For speed vs.
ATtiny25/45/85 25.3 ATtiny85 Speed (MHz) (1) 10 20 Notes: Supply Voltage (V) 1.8 – 5.5 2.7 – 5.5 Temperature Range Industrial (-40°C to +85°C) (4) Industrial (-40°C to +85°C) (4) Package (2) Ordering Code (3) 8P3 ATtiny85V-10PU 8S2 ATtiny85V-10SU ATtiny85V-10SUR ATtiny85V-10SH 20M1 ATtiny85V-10MU ATtiny85V-10MUR 8P3 ATtiny85-20PU 8S2 ATtiny85-20SU ATtiny85-20SUR ATtiny85-20SH 20M1 ATtiny85-20MU ATtiny85-20MUR 1. For speed vs. supply voltage, see section 21.3 “Speed” on page 168. 2.
26. Packaging Information 26.1 8P3 E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A SYMBOL MIN NOM A b2 b3 b 4 PLCS Side View L 0.210 NOTE 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 0.100 BSC eA 0.300 BSC 0.115 3 3 e L Notes: MAX 0.130 4 0.150 2 1.
ATtiny25/45/85 26.2 8S2 C 1 E E1 L N θ TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A SYMBOL A1 D SIDE VIEW MAX NOM NOTE 1.70 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 θ 0° 8° e Notes: 1. 2. 3. 4. MIN A 2.16 1.27 BSC 2 3 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
26.3 S8S1 1 E1 E N Top View e b A A1 D Side View C L End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX E 5.79 6.20 E1 3.81 3.99 A 1.35 1.75 A1 0.1 0.25 D 4.80 4.98 C 0.17 0.25 b 0.31 0.51 L 0.4 1.27 e NOTE 1.27 BSC 0o 8o Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc. 7/28/03 R 214 2325 Orchard Parkway San Jose, CA 95131 TITLE S8S1, 8-lead, 0.
ATtiny25/45/85 26.4 8X C 1 E1 End View E L Top View e Ø b COMMON DIMENSIONS (Unit of Measure = mm) A A1 MAX 1.05 1.10 1.20 A1 0.05 0.10 0.15 b 0.25 – 0.30 C – 0.127 – D 2.90 3.05 3.10 E1 4.30 4.40 4.50 E 6.20 6.40 6.60 A D Side View MIN NOM SYMBOL e NOTE 0.65 TYP L 0.50 0.60 0.70 Ø 0o – 8o Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153AC. 4/14/05 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8X, 8-lead, 4.
26.5 20M1 D 1 Pin 1 ID 2 SIDE VIEW E 3 TOP VIEW A2 D2 A1 A 0.08 1 2 Pin #1 Notch (0.20 R) 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 b L e BOTTOM VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 b 0.18 D D2 E2 L 0.23 0.30 4.00 BSC 2.45 2.60 2.75 4.00 BSC 2.45 e Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. NOTE 0.20 REF E Note: C 2.60 2.75 0.50 BSC 0.35 0.40 0.
ATtiny25/45/85 27. Errata 27.1 Errata ATtiny25 The revision letter in this section refers to the revision of the ATtiny25 device. 27.1.1 Rev D and E No known errata. 27.1.2 Rev B and C • EEPROM read may fail at low supply voltage / low clock frequency 1. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data.
27.2.3 Rev B and C • • • • PLL not locking EEPROM read from application code does not work in Lock Bit Mode 3 EEPROM read may fail at low supply voltage / low clock frequency Timer Counter 1 PWM output generation on OC1B- XOC1B does not work correctly 1. PLL not locking When at frequencies below 6.0 MHz, the PLL will not lock Problem fix / Workaround When using the PLL, run at 6.0 MHz or higher. 2.
ATtiny25/45/85 – The EEPROM is read before entering power down. – VCC is 4.5 volts or higher. Problem fix / Workaround – When using external clock, avoid setting the clock pin as Output. – Do not read the EEPROM if power down power consumption is important. – Use VCC lower than 4.5 Volts. 2. DebugWIRE looses communication when single stepping into interrupts When receiving an interrupt during single stepping, debugwire will loose communication.
27.3 Errata ATtiny85 The revision letter in this section refers to the revision of the ATtiny85 device. 27.3.1 Rev B and C No known errata. 27.3.2 Rev A • EEPROM read may fail at low supply voltage / low clock frequency 1. EEPROM read may fail at low supply voltage / low clock frequency Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data. Problem Fix/Workaround Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V.
ATtiny25/45/85 28. Datasheet Revision History 28.1 Rev. 2586N-04/11 1. Added: – Section “Capacitive Touch Sensing” on page 6. 2. Updated: – Document template. – Removed “Preliminary” on front page. All devices now final and in production. – Section “Limitations” on page 37. – Program example on page 51. – Section “Overview” on page 126. – Table 17-4 on page 139. – Section “Limitations of debugWIRE” on page 144. – Section “Serial Programming Algorithm” on page 156. – Table 21-7 on page 171.
– Table 20-16, “High-voltage Serial Programming Instruction Set for ATtiny25/45/85,” on page 163 – Table 21-1, “DC Characteristics. TA = -40°C to +85°C,” on page 166, notes adjusted – Table 21-11, “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 5.5V (Unless Otherwise Noted),” on page 175, added tSLIV – Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0]. 28.4 Rev. 2586K-01/08 1. Updated Document Template. 2.
ATtiny25/45/85 – “Compare Mode Select in PWM Mode” on page 101 – “DC Characteristics. TA = -40°C to +85°C” on page 166 – “Calibration Accuracy of Internal RC Oscillator” on page 169 – “ADC Characteristics” on page 172 7. Updated Code Example in Section: – “Write” on page 17 8.
14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 28.6 Rev. 2586I-09/06 1. 2. 3. 4. 5. 6. 7. 224 Updated “Bit 0” in “PRR – Power Reduction Register” on page 39. Added footnote to Table 8-3 on page 48. Updated Table 10-5 on page 65. Deleted “Bits 7, 2” in “MCUCR – MCU Control Register” on page 66. Updated and moved section “Timer/Counter0 Prescaler and Clock Sources”, now located on page 68.
ATtiny25/45/85 8. 9. 10. 11. 12. 13. 28.7 Rev. 2586H-06/06 1. 2. 3. 28.8 Updated “Calibrated Internal Oscillator” on page 27. Updated Table 6.5.1 on page 32. Added Table 21-2 on page 169. Rev. 2586G-05/06 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 28.9 Updated Features in “USI – Universal Serial Interface” on page 111. Updated Code Example in “SPI Master Operation Example” on page 113 and “SPI Slave Operation Example” on page 114. Updated “Analog Comparator Multiplexed Input” on page 123.
28.11 Rev. 2586D-02/06 1. 2. 3. 4. 5. 6. 7. 8. 9. Updated Table 6-13 on page 30, Table 6-10 on page 29, Table 6-3 on page 26, Table 6-9 on page 29, Table 6-5 on page 27, Table 9-1 on page 50,Table 17-4 on page 139, Table 20-16 on page 163, Table 21-8 on page 172. Updated “Timer/Counter1 in PWM Mode” on page 89. Updated text “Bit 2 – TOV1: Timer/Counter1 Overflow Flag” on page 96. Updated values in “DC Characteristics” on page 166. Updated “Register Summary” on page 205.
ATtiny25/45/85 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 2 Overview ................................................................................................... 4 2.1 3 4 5 6 7 Pin Descriptions .................................................................................................
8 9 7.1 Sleep Modes ....................................................................................................35 7.2 Software BOD Disable .....................................................................................36 7.3 Power Reduction Register ...............................................................................37 7.4 Minimizing Power Consumption ......................................................................37 7.5 Register Description .......................
ATtiny25/45/85 13 8-bit Timer/Counter1 in ATtiny15 Mode ............................................... 98 13.1 Timer/Counter1 Prescaler ...............................................................................98 13.2 Counter and Compare Units ............................................................................98 13.3 Register Description ......................................................................................103 14 Dead Time Generator ......................................
18.5 Limitations of debugWIRE .............................................................................144 18.6 Register Description ......................................................................................144 19 Self-Programming the Flash ............................................................... 145 19.1 Performing Page Erase by SPM ....................................................................145 19.2 Filling the Temporary Buffer (Page Loading) .........................
ATtiny25/45/85 22.5 Pin Pull-up .....................................................................................................184 22.6 Pin Driver Strength ........................................................................................187 22.7 Pin Threshold and Hysteresis ........................................................................191 22.8 BOD Threshold ..............................................................................................194 22.
vi 28.11 Rev. 2586D-02/06 .........................................................................................226 28.12 Rev. 2586C-06/05 .........................................................................................226 28.13 Rev. 2586B-05/05 ..........................................................................................226 28.14 Rev. 2586A-02/05 ..........................................................................................
ATtiny25/45/85 vii 2586N–AVR–04/11
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