Datasheet

117
2586N–AVR–04/11
ATtiny25/45/85
enables its output. If the bit is set, a master read operation is in progress (i.e., the slave
drives the SDA line) The slave can hold the SCL line low after the acknowledge (E).
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is
given by the master (F), or a new start condition is given.
If the slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the master does a read operation it must terminate the operation by forcing the
acknowledge bit low after the last byte transmitted.
15.3.5 Start Condition Detector
The start condition detector is shown in Figure 15-6. The SDA line is delayed (in the range of 50
to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled
in two-wire mode.
Figure 15-6. Start Condition Detector, Logic Diagram
The start condition detector is working asynchronously and can therefore wake up the processor
from power-down sleep mode. However, the protocol used might have restrictions on the SCL
hold time. Therefore, when using this feature the oscillator start-up time (set by CKSEL fuses,
see “Clock Systems and their Distribution” on page 23) must also be taken into consideration.
Refer to the description of the USISIF bit on page 119 for further details.
15.3.6 Clock speed considerations
Maximum frequency for SCL and SCK is f
CK
/ 2. This is also the maximum data transmit and
receive rate in both two- and three-wire mode. In two-wire slave mode the Two-wire Clock Con-
trol Unit will hold the SCL low until the slave is ready to receive more data. This may reduce the
actual data rate in two-wire mode.
15.4 Alternative USI Usage
The flexible design of the USI allows it to be used for other tasks when serial communication is
not needed. Below are some examples.
15.4.1 Half-Duplex Asynchronous Data Transfer
Using the USI Data Register in three-wire mode it is possible to implement a more compact and
higher performance UART than by software, only.
15.4.2 4-Bit Counter
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will increment the counter value.
SDA
SCL
Write( USISIF)
CLOCK
HOLD
USISIF
DQ
CLR
DQ
CLR