Datasheet

107
2586N–AVR–04/11
ATtiny25/45/85
• Bit 6 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data
value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchroniza-
tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A
are set (one), the Timer/Counter1 A compare match interrupt is executed.
• Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is
cleared, after synchronization clock cycle, by writing a logical one to the flag. When the SREG I-
bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the
Timer/Counter1 Overflow interrupt is executed.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
13.3.8 PLLCSR – PLL Control and Status Register
• Bits 6:3 – Res : Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and always read as zero.
• Bit 2 – PCKE: PCK Enable
The bit PCKE is always set in the ATtiny15 compatibility mode.
• Bit 1 – PLLE: PLL Enable
The PLL is always enabled in the ATtiny15 compatibility mode.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be
ignored during initial PLL lock-in sequence when PLL frequency overshoots and undershoots,
before reaching steady state. The steady state is obtained within 100 µs. After PLL lock-in it is
recommended to check the PLOCK bit before enabling PCK for Timer/Counter1.
Bit 76543210
0x27
LSM – – – – PCKE PLLE PLOCK PLLCSR
Read/Write R/W R R R R R/W R/W R
Initial value 0 0 0 0 0 0 0/1 0