Datasheet

69
ATmega8(L)
2486M–AVR–12/03
Timer/Counter Timing
Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore
shown as a clock enable signal in the following figures. The figures include information
on when Interrupt Flags are set. Figure 28 contains timing data for basic Timer/Counter
operation. The figure shows the count sequence close to the MAX value.
Figure 28. Timer/Counter Timing Diagram, No Prescaling
Figure 29 shows the same timing data, but with the prescaler enabled.
Figure 29. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)