Datasheet

68
ATmega8(L)
2486M–AVR–12/03
Timer/Counter Clock
Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the clock select logic which is controlled by the clock select
(CS02:0) bits located in the Timer/Counter Control Register (TCCR0). For details on
clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on
page 72.
Counter Unit The main part of the 8-bit Timer/Counter is the programmable counter unit. Figure 27
shows a block diagram of the counter and its surroundings.
Figure 27. Counter Unit Block Diagram
Signal description (internal signals):
count Increment TCNT0 by 1.
clk
Tn
Timer/Counter clock, referred to as clk
T0
in the following.
max Signalize that TCNT0 has reached maximum value.
The counter is incremented at each timer clock (clk
T0
). clk
T0
can be generated from an
external or internal clock source, selected by the clock select bits (CS02:0). When no
clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value
can be accessed by the CPU, regardless of whether clk
T0
is present or not. A CPU write
overrides (has priority over) all counter clear or count operations.
Operation The counting direction is always up (incrementing), and no counter clear is performed.
The counter simply overruns when it passes its maximum 8-bit value (MAX = 0xFF) and
then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow
Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The
TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared.
However, combined with the timer overflow interrupt that automatically clears the TOV0
Flag, the timer resolution can be increased by software. A new counter value can be
written anytime.
DATA BUS
TCNTn Control Logic
count
TOVn
(Int. Req.)
Clock Select
max
Tn
Edge
Detector
( From Prescaler )
clk
Tn