Datasheet

37
ATmega8(L)
2486M–AVR–12/03
Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-
tion level is defined in Table 15. The POR is activated whenever V
CC
is below the
detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reach-
ing the Power-on Reset threshold voltage invokes the delay counter, which determines
how long the device is kept in RESET after V
CC
rise. The RESET signal is activated
again, without any delay, when V
CC
decreases below the detection level.
Figure 15. MCU Start-up, RESET Tied to V
CC
Figure 16. MCU Start-up, RESET Extended Externally
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
V
CC