Datasheet

154
ATmega8(L)
2486M–AVR–12/03
• Bit 5:4 – UPM1:0: Parity Mode
These bits enable and set type of Parity Generation and Check. If enabled, the Trans-
mitter will automatically generate and send the parity of the transmitted data bits within
each frame. The Receiver will generate a parity value for the incoming data and com-
pare it to the UPM0 setting. If a mismatch is detected, the PE Flag in UCSRA will be set.
• Bit 3 – USBS: Stop Bit Select
This bit selects the number of stop bits to be inserted by the trAnsmitter. The Receiver
ignores this setting.
• Bit 2:1 – UCSZ1:0: Character Size
The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits
(Character Size) in a frame the Receiver and Transmitter use.
• Bit 0 – UCPOL: Clock Polarity
Table 56. UPM Bits Settings
UPM1 UPM0 Parity Mode
0 0 Disabled
0 1 Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
Table 57. USBS Bit Settings
USBS Stop Bit(s)
0 1-bit
1 2-bit
Table 58. UCSZ Bits Settings
UCSZ2 UCSZ1 UCSZ0 Character Size
0 0 0 5-bit
0 0 1 6-bit
0 1 0 7-bit
0 1 1 8-bit
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 9-bit