Datasheet

ATmega8(L)

2486M–AVR–12/03

Timer/Counter Interrupt Mask

• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable

When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is

executed if a Compare Match in Timer/Counter2 occurs (i.e., when the OCF2 bit is set in

the Timer/Counter Interrupt Flag Register – TIFR).

• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if

an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set in the

Timer/Counter Interrupt Flag Register – TIFR).

Timer/Counter Interrupt Flag

• Bit 7 – OCF2: Output Compare Flag 2

The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2

and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when

executing the corresponding interrupt Handling Vector. Alternatively, OCF2 is cleared

by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Com-

pare Match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare

Match Interrupt is executed.

• Bit 6 – TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared

by hardware when executing the corresponding interrupt Handling Vector. Alternatively,

TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2

(Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the

Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when

Timer/Counter2 changes counting direction at 0x00.

Bit 7 6 5 4 3 2 1 0

OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 TIMSK

Read/Write R/W R/W R/W R/W R/W R/W R R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 TIFR

Read/Write R/W R/W R/W R/W R/W R/W R R/W

Initial Value 0 0 0 0 0 0 0 0