Datasheet

100
ATmega8(L)
2486M–AVR–12/03
Input Capture Register 1 –
ICR1H and ICR1L
The Input Capture is updated with the counter (TCNT1) value each time an event occurs
on the ICP1 pin (or optionally on the Analog Comparator Output for Timer/Counter1).
The Input Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes
are read simultaneously when the CPU accesses these registers, the access is per-
formed using an 8-bit temporary High byte Register (TEMP). This temporary register is
shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 77.
Timer/Counter Interrupt Mask
Register – TIMSK
(1)
Note: 1. This register contains interrupt control bits for several Timer/Counters, but only
Timer1 bits are described in this section. The remaining bits are described in their
respective timer sections.
• Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Input Capture Interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 44) is executed when the ICF1
Flag, located in TIFR, is set.
• Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 44) is executed when the
OCF1A Flag, located in TIFR, is set.
• Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The
corresponding Interrupt Vector (see “Interrupts” on page 44) is executed when the
OCF1B Flag, located in TIFR, is set.
• Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 44) is executed when the TOV1 Flag, located
in TIFR, is set.
Bit 7 6 5 4 3 2 1 0
ICR1[15:8] ICR1H
ICR1[7:0] ICR1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1
–
TOIE0 TIMSK
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial Value 0 0 0 0 0 0 0 0