Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 130 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories – 8K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming
Pin Configurations PDIP (RESET) PC6 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK/T0) PD4 VCC GND (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) PC1 (ADC1) PC0 (ADC0) GND AREF AVCC PB5 (SCK) PB4 (MISO) PB3 (MOSI/OC2) PB2 (SS/OC1B) PB1 (OC1A) 32 31 30 29 28 27 26 25 PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3
ATmega8(L) Overview The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 1.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega8(L) Pin Descriptions VCC Digital supply voltage. GND Ground. Port B (PB7..PB0) XTAL1/ XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated.
AVCC AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that Port C (5..4) use digital supply voltage, VCC. AREF AREF is the analog reference pin for the A/D Converter. ADC7..6 (TQFP and MLF Package Only) In the TQFP and MLF package, ADC7..6 serve as analog inputs to the A/D converter.
ATmega8(L) AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 2.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register.
ATmega8(L) Arithmetic Logic Unit – ALU The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions.
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega8(L) The X-register, Y-register and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as described in Figure 4. Figure 4.
Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
ATmega8(L) of the boot Flash section by setting the Interrupt Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 44 for more information. The Reset Vector can also be moved to the start of the boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write SelfProgramming” on page 206. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following example.
ATmega8(L) AVR ATmega8 Memories This section describes the different memories in the ATmega8. The AVR architecture has two main memory spaces, the Data memory and the Program Memory space. In addition, the ATmega8 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. In-System Reprogrammable Flash Program Memory The ATmega8 contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage.
SRAM Data Memory Figure 8 shows how the ATmega8 SRAM Memory is organized. The lower 1120 Data memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 1024 locations address the internal data SRAM. The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment.
ATmega8(L) Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 9. Figure 9. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address Valid Write Data WR Read Data RD Memory Vccess Instruction EEPROM Data Memory Next Instruction The ATmega8 contains 512 bytes of data EEPROM memory.
The EEPROM Address Register – EEARH and EEARL Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 – – – – – – – EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 X X X X X X X X X • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega8 and will always read as zero. • Bits 8..0 – EEAR8..
ATmega8(L) value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
ATmega8(L) The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC Reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
ATmega8(L) System Clock and Clock Options Clock Systems and their Distribution Figure 10 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 31. The clock systems are detailed Figure 10. Figure 10.
Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. The Asynchronous Timer/Counter uses the same XTAL pins as the CPU main clock but requires a CPU main clock frequency of more than four times the Oscillator frequency.
ATmega8(L) Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 11. Either a quartz crystal or a ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate a full rail-to-rail swing on the output.
Table 5. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1..0 Start-up Time from Power-down and Power-save 0 00 258 CK(1) 4.1 ms Ceramic resonator, fast rising power 0 01 258 CK(1) 65 ms Ceramic resonator, slowly rising power 0 10 1K CK(2) – Ceramic resonator, BOD enabled 0 11 1K CK(2) 4.1 ms Ceramic resonator, fast rising power 1 00 1K CK(2) 65 ms Ceramic resonator, slowly rising power 1 01 16K CK – Crystal Oscillator, BOD enabled 1 10 16K CK 4.
ATmega8(L) External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 12 can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22 pF. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND, thereby removing the need for an external capacitor.
Calibrated Internal RC Oscillator The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. All frequencies are nominal values at 5V and 25°C. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 9. If selected, it will operate with no external components. The CKOPT Fuse should always be unprogrammed when using this clock option.
ATmega8(L) Oscillator Calibration Register – OSCCAL Bit Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7..0 – CAL7..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the Internal Oscillator to remove process variations from the Oscillator frequency.
External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 13. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND. Figure 13. External Clock Drive Configuration EXTERNAL CLOCK SIGNAL When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 12. Table 12.
ATmega8(L) Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the five sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed.
Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Twowire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
ATmega8(L) asynchronous timer should be considered undefined after wake-up in Power-save mode if AS2 is 0. This sleep mode basically halts all clocks except clkASY, allowing operation only of asynchronous modules, including Timer/Counter 2 if clocked asynchronously. Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode.
Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 38 for details on how to configure the Brown-out Detector.
ATmega8(L) System Control and Reset Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the boot section or vice versa.
Figure 14. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Control and Status Register (MCUCSR) Brown-Out Reset Circuit BODEN BODLEVEL Pull-up Resistor SPIKE FILTER Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] Table 15. Reset Characteristics Symbol VPOT Condition Min Typ Max Units Power-on Reset Threshold Voltage (rising)(1) 1.4 2.3 V Power-on Reset Threshold Voltage (falling) 1.3 2.3 V 0.9 VCC 1.
ATmega8(L) Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 15. The POR is activated whenever V CC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 15) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V RST on its positive edge, the delay counter starts the MCU after the time-out period tTOUT has expired. Figure 17.
ATmega8(L) Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the time-out period tTOUT. Refer to page 41 for details on operation of the Watchdog Timer. Figure 19. Watchdog Reset During Operation CC CK MCU Control and Status Register – MCUCSR The MCU Control and Status Register provides information on which reset source caused an MCU Reset.
Internal Voltage Reference ATmega8 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 16. To save power, the reference is not always turned on.
ATmega8(L) Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 17 on page 42. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
• Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2.
ATmega8(L) Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing the Watchdog Timer configuration differs slightly between the safety levels. Separate procedures are described for each level.
Interrupts Interrupt Vectors in ATmega8 This section describes the specifics of the interrupt handling performed by the ATmega8. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Table 18. Reset and Interrupt Vectors Vector No.
ATmega8(L) Table 19. Reset and Interrupt Vectors Placement BOOTRST(1) IVSEL 1 Reset Address Interrupt Vectors Start Address 0 0x000 0x001 1 1 0x000 Boot Reset Address + 0x001 0 0 Boot Reset Address 0x001 0 1 Boot Reset Address Boot Reset Address + 0x001 Note: 1. The Boot Reset Address is shown in Table 82 on page 217. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed.
When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code $000 ; $001 rjmp RESET:ldi Comments RESET ; Reset handler r16,high(RAMEND); Main program start $002 out SPH,r16 ; Set Stack Pointer to top of RAM $003 ldi r16,low(RAMEND) $004 out SPL,r16 $005 sei $006 ; Enable inter
ATmega8(L) When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes, and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code Comments ; Moving Interrupts Between Application and Boot Space General Interrupt Control Register – GICR .org $c00 $c00 $c01 rjmp rjmp RESET EXT_INT0 ; Reset handler ; IRQ0 Handler $c02 rjmp EXT_INT1 ; IRQ1 Handler ...
• Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
ATmega8(L) I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 shows a functional description of one I/O port pin, here generically called Pxn. Figure 22.
ATmega8(L) When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports.
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
ATmega8(L) The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
Unconnected pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATmega8(L) Table 21 summarizes the function of the overriding signals. The pin and port indexes from Figure 25 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 21. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
Special Function IO Register – SFIOR Bit 7 6 5 4 3 2 1 0 ACME PUD PSR2 PSR10 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 2 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 50 for more details about this feature.
ATmega8(L) inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0. • SCK – Port B, Bit 5 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5.
Table 23. Overriding Signals for Alternate Functions in PB7..
ATmega8(L) Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 25. Table 25.
PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power. • ADC0 – Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power. Table 26 and Table 27 relate the alternate functions of Port C to the overriding signals shown in Figure 25 on page 54. Table 26. Overriding Signals for Alternate Functions in PC6..
ATmega8(L) Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 28. Table 28.
Table 29 and Table 30 relate the alternate functions of Port D to the overriding signals shown in Figure 25 on page 54. Table 29. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/AIN1 PD6/AIN0 PD5/T1 PD4/XCK/T0 PUOE 0 0 0 0 PUO 0 0 0 0 OOE 0 0 0 0 OO 0 0 0 0 PVOE 0 0 0 UMSEL PVO 0 0 0 XCK OUTPUT DIEOE 0 0 0 0 DIEO 0 0 0 0 DI – – T1 INPUT XCK INPUT / T0 INPUT AIO AIN1 INPUT AIN0 INPUT – – Table 30.
ATmega8(L) Register Description for I/O Ports The Port B Data Register – PORTB The Port B Data Direction Register – DDRB The Port B Input Pins Address – PINB The Port C Data Register – PORTC The Port C Data Direction Register – DDRC The Port C Input Pins Address – PINC The Port D Data Register – PORTD The Port D Data Direction Register – DDRD The Port D Input Pins Address – PIND Bit 7 6 5 4 3 2 1 0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Read/Write R/W R/W R/W R
External Interrupts The external interrupts are triggered by the INT0, and INT1 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register – MCUCR.
ATmega8(L) • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 32. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt.
General Interrupt Flag Register – GIFR Bit 7 6 5 4 3 2 1 INTF1 INTF0 – – – – – 0 – Read/Write R/W R/W R R R R R R Initial Value 0 0 0 0 0 0 0 0 GIFR • Bit 7 – INTF1: External Interrupt Flag 1 When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
ATmega8(L) 8-bit Timer/Counter0 Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Frequency Generator • External Event Counter • 10-bit Clock Prescaler Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 26. For the actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold.
Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 72. Counter Unit The main part of the 8-bit Timer/Counter is the programmable counter unit.
ATmega8(L) Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clk T0 ) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 28 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value. Figure 28.
8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Bit 7 6 5 4 3 2 1 0 – – – – – CS02 CS01 CS00 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0 • Bit 2:0 – CS02:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter. Table 34. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped).
ATmega8(L) Timer/Counter Interrupt Flag Register – TIFR Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, TOV0 is cleared by writing a logic one to the flag.
Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
ATmega8(L) Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem).
16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e.
ATmega8(L) Figure 32. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int. Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCFnA (Int. Req.) Waveform Generation = OCnA DATA BUS OCRnA OCFnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: Registers TCCRnB 1.
set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins (see “Analog Comparator” on page 190). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
ATmega8(L) Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. The 16-bit timer has a single 8-bit register for temporary storing of the High byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within the 16-bit timer. Accessing the Low byte triggers the 16-bit read or write operation.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega8(L) The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS12:0) bits located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 72. Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
ATmega8(L) The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare Outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 86.
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the Low byte (ICR1L) and then the High byte (ICR1H). When the Low byte is read the High byte is copied into the High byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value.
ATmega8(L) (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle.
update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly.
ATmega8(L) Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The waveform generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 36 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
Compare Output Mode and Waveform Generation The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the waveform generator that no action on the OC1x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 36 on page 95. For fast PWM mode refer to Table 37 on page 96, and for phase correct and phase and frequency correct PWM refer to Table 38 on page 96.
ATmega8(L) Figure 37. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
quency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
ATmega8(L) ing at 0x0000 before the Compare Match can occur. The OCR1A Register, however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP.
OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11).
ATmega8(L) period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the Phase and Frequency Correct mode instead of the Phase Correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
(WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 40. The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs.
ATmega8(L) to 3. See Table 38 on page 96. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at Compare Match between OCR1x and TCNT1 when the counter decrements.
Figure 42. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 43 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
ATmega8(L) Figure 44.
Table 37 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 37. Compare Output Mode, Fast PWM(1) COM1A1/ COM1B1 COM1A0/ COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
ATmega8(L) what type of waveform generation to be used, see Table 39. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 86.) Table 39.
Timer/Counter 1 Control Register B – TCCR1B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1B • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture Pin (ICP1) is filtered.
ATmega8(L) If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting.
Input Capture Register 1 – ICR1H and ICR1L Bit 7 6 5 4 3 2 1 0 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator Output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size.
ATmega8(L) Timer/Counter Interrupt Flag Register – TIFR(1) Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 Note: TIFR 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections.
8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
ATmega8(L) Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units.
Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 46 shows a block diagram of the counter and its surrounding environment. Figure 46. Counter Unit Block Diagram TOVn (Int. Req.) DATA BUS TOSC1 count TCNTn clear Control Logic clk Tn Prescaler T/C Oscillator direction BOTTOM TOSC2 TOP clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement.
ATmega8(L) Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF2 Flag is automatically cleared when the interrupt is executed.
Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the OCF2 Flag or reload/clear the timer, but the OC2 pin will be updated as if a real Compare Match had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled).
ATmega8(L) Compare Match Output Unit The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the OC2 pin output source. Figure 48 shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
Compare Output Mode and Waveform Generation The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM21:0 = 0 tells the waveform generator that no action on the OC2 Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 43 on page 116. For fast PWM mode, refer to Table 44 on page 116, and for phase correct PWM refer to Table 45 on page 116.
ATmega8(L) Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events.
Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM.
ATmega8(L) The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OC nPWM = -----------------N ⋅ 256 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle.
Figure 51. Phase Correct PWM Mode, Timing Diagram OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin.
ATmega8(L) • Timer/Counter Timing Diagrams The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In Asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock.
Figure 54. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 55 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 55.
ATmega8(L) 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR2 Bit 7 6 5 4 3 2 1 0 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR2 • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode.
Table 43. Compare Output Mode, Non-PWM Mode COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected. 0 1 Toggle OC2 on Compare Match 1 0 Clear OC2 on Compare Match 1 1 Set OC2 on Compare Match Table 44 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 44. Compare Output Mode, Fast PWM Mode(1) COM21 COM20 0 0 Normal port operation, OC2 disconnected.
ATmega8(L) • Bit 2:0 – CS22:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Table 46. Table 46. Clock Select Bit Description Timer/Counter Register – TCNT2 CS22 CS21 CS20 0 0 0 No clock source (Timer/Counter stopped).
• Bit 2 – TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. • Bit 1 – OCR2UB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set.
ATmega8(L) changes are effective. This is particularly important if the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a Compare Match interrupt, and the MCU will not wake up.
Timer/Counter Interrupt Mask Register – TIMSK Bit 7 6 5 4 3 2 1 0 OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK • Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled.
ATmega8(L) Figure 56. Prescaler for Timer/Counter2 clkT2S PSR2 clkT2S/1024 clkT2S/256 clkT2S/8 AS2 clkT2S/128 10-BIT T/C PRESCALER Clear TOSC1 clkT2S/64 clkI/O clkT2S/32 Timer/Counter Prescaler 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clk I/O. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin.
Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8 and peripheral devices or between several AVR devices.
ATmega8(L) When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested.
The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
ATmega8(L) The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega8(L) be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 59 and Figure 60 for an example. The CPOL functionality is summarized below: Table 48.
SPI Status Register – SPSR Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag.
ATmega8(L) Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 59 and Figure 60. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 48 and Table 49, as done below: Table 51.
USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly-flexible serial communication device.
ATmega8(L) The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock generator, Transmitter and Receiver. Control Registers are shared by all units. The clock generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (transfer clock) pin is only used by synchronous transfer mode.
Figure 62. Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector UCPOL DDR_XCK 0 UMSEL 1 xcko txclk 1 1 0 rxclk Signal description: Internal Clock Generation – The Baud Rate Generator txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. (Internal Signal) xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
ATmega8(L) Table 52.
Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 63.
ATmega8(L) Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.
Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRH, r17 out UBRRL, r16 ; Enable Receiver and Transmitter ldi r16, (1<>8); UBRRL = (unsigned char)baud; /* Enable Receiver and Transmitter */ UCSRB = (1<
ATmega8(L) Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
Sending Frames with 9 Data Bits If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the Low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
ATmega8(L) interrupt-driven data transmission is used, the Data Register empty Interrupt routine must either write new data to UDR in order to clear UDRE or disable the Data Register empty Interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer.
Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock.
ATmega8(L) Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and PE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR, and PE bits, which all are stored in the FIFO, will change.
The following code example shows a simple USART receive function that handles both 9-bit characters and the status bits.
ATmega8(L) Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero.
Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits.
ATmega8(L) (U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). Figure 65. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated.
Figure 67. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting.
ATmega8(L) Table 53. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) D# (Data+Parity Bit) Rslow(%) Rfast(%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93,20 106,67 +6.67/-6.8 ± 3.0 6 94,12 105,79 +5.79/-5.88 ± 2.0 7 94,81 105,11 +5.11/-5.19 ± 2.0 8 95,36 104,58 +4.58/-4.54 ± 2.0 9 95,81 104,14 +4.14/-4.19 ± 1.5 10 96,17 103,78 +3.78/-3.83 ± 1.5 Table 54.
Multi-processor Communication Mode Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus.
ATmega8(L) Accessing UBRRH/UCSRC Registers The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. Write Access When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is zero during a write operation, the UBRRH value will be updated.
Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex operation. However, in most applications, it is rarely necessary to read any of these registers. The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH Register contents. If the register location was read in previous system clock cycle, reading the register in the current clock cycle will return the UCSRC contents.
ATmega8(L) The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set. Data written to UDR when the UDRE Flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the TxD pin. The receive buffer consists of a two level FIFO.
This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. • Bit 0 – MPCM: Multi-processor Communication Mode This bit enables the Multi-processor Communication mode.
ATmega8(L) TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR. USART Control and Status Register C – UCSRC Bit 7 6 5 4 3 2 1 0 URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 0 0 0 0 1 1 0 UCSRC The UCSRC Register shares the same I/O location as the UBRRH Register.
• Bit 5:4 – UPM1:0: Parity Mode These bits enable and set type of Parity Generation and Check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE Flag in UCSRA will be set. Table 56.
ATmega8(L) This bit is used for Synchronous mode only. Write this bit to zero when Asynchronous mode is used. The UCPOL bit sets the relationship between data output change and data input sample, and the synchronous clock (XCK). Table 59.
Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 60. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
ATmega8(L) Table 61. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.
Table 62. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.
ATmega8(L) Table 63. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.
Two-wire Serial Interface Features • • • • • • • • • • Two-wire Serial Interface Bus Definition The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines.
ATmega8(L) Electrical Interconnection As depicted in Figure 68, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero.
Figure 70. START, REPEATED START and STOP conditions SDA SCL STOP START Address Packet Format START REPEATED START STOP All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed. When a Slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle.
ATmega8(L) Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled.
Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: • An algorithm must be implemented allowing only one of the masters to complete the transmission.
ATmega8(L) Figure 75. Arbitration Between Two Masters START SDA from Master A Master A Loses Arbitration, SDAA SDA SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit. • A STOP condition and a data bit. • A REPEATED START and a STOP condition. It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 76. All registers drawn in a thick line are accessible through the AVR data bus. Figure 76.
ATmega8(L) Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period.
Interrupt Flag is asserted. At all other times, the TWSR contains a special status code indicating that no relevant status information is available. As long as the TWINT Flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue. The TWINT Flag is set in the following situations: • After the TWI has transmitted a START/REPEATED START condition. • After the TWI has transmitted SLA+R/W.
ATmega8(L) The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in Master Receiver or Slave Receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the Twowire Serial Bus temporarily.
TWI Status Register – TWSR Bit 7 6 5 4 3 2 1 0 TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 Read/Write R R R R R R R/W R/W Initial Value 1 1 1 1 1 0 0 0 TWSR • Bits 7..3 – TWS: TWI Status These 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different status codes are described later in this section. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value.
ATmega8(L) TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 0 TWAR The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver, and not needed in the Master modes. In multimaster systems, TWAR must be set in masters which can be addressed as Slaves by other Masters.
Application Action Figure 77. Interfacing the Application to the TWI in a Typical Transmission 1. Application writes to TWCR to initiate transmission of START TWI Hardware Action TWI bus 3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, makin sure that TWINT is written to one, and TWSTA is written to zero. START 2. TWINT set. Status code indicates START condition sent SLA+W 5.
ATmega8(L) described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet. 6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has successfully been sent.
Assembly Code Example 1 ldi r16, (1<
ATmega8(L) Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
Master Transmitter Mode In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver (see Figure 78). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
ATmega8(L) This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition.
Figure 79.
ATmega8(L) Master Receiver Mode In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter (see Figure 80). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered.
After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Table 67.
ATmega8(L) Figure 81.
The upper 7 bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address.
ATmega8(L) Table 68.
Figure 83. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
ATmega8(L) Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver (see Figure 84). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 84. Data Transfer in Slave Transmitter Mode VCC Device 1 Device 2 SLAVE TRANSMITTER MASTER RECEIVER ........
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up and until the TWINT Flag is cleared (by writing it to one). Further data transmission will be carried out as normal, with the AVR clocks running as normal.
ATmega8(L) Figure 85. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted.
Combining Several TWI Modes In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated. 2. The EEPROM must be instructed what location should be read. 3. The reading must be performed. 4. The transfer must be finished. Note that data is transmitted both from Master to Slave and vice versa.
ATmega8(L) • Two or more masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the masters will know about the bus contention. • Two or more masters are accessing the same Slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration.
Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega8(L) Analog Comparator Control and Status Register – ACSR Bit 7 6 5 4 3 2 1 0 ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 N/A 0 0 0 0 0 ACSR • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. Analog Comparator Multiplexed Input It is possible to select any of the ADC7..0(1) pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently the ADC must be switched off to utilize this feature.
ATmega8(L) Analog-to-Digital Converter Features • • • • • • • • • • • • • 10-bit Resolution (8-bit Accuracy on ADC4 and ADC5) 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 65 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution 6 Multiplexed Single Ended Input Channels 2 Additional Multiplexed Single Ended Input Channels (TQFP and MLF Package only) Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
Figure 90. Analog to Digital Converter Block Schematic Operation ADC CONVERSION COMPLETE IRQ 15 ADC[9:0] ADPS1 ADPS0 ADPS2 ADIF ADFR ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL. & STATUS REGISTER (ADCSRA) MUX0 MUX2 MUX1 MUX3 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS MUX DECODER CHANNEL SELECTION PRESCALER AVCC CONVERSION LOGIC INTERNAL 2.
ATmega8(L) If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost.
takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In single conversion mode, ADSC is cleared simultaneously.
ATmega8(L) Figure 94. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH MSB of Result ADCL LSB of Result Sample &Hold Conversion Complete MUX and REFS Update Table 73. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) Extended conversion 13.5 25 Normal conversions, single ended 1.
ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.
ATmega8(L) Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 95. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path).
Analog Ground Plane PC2 (ADC2) PC3 (ADC3) PC4 (ADC4/SDA) PC5 (ADC5/SCL) VCC GND Figure 96. ADC Power Connections PC1 (ADC1) PC0 (ADC0) ADC7 10µH GND AREF 100nF ADC6 AVCC PB5 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
ATmega8(L) • Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 98. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.
Figure 100. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 ADC Conversion Result VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB. • Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code.
ATmega8(L) Table 74. Voltage Reference Selections for ADC • REFS1 REFS0 Voltage Reference Selection 0 0 AREF, Internal Vref turned off 0 1 AVCC with external capacitor at AREF pin 1 0 Reserved 1 1 Internal 2.56V Voltage Reference with external capacitor at AREF pin Bit 5 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted.
ADC Control and Status Register A – ADCSRA Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATmega8(L) • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 76.
Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
ATmega8(L) Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update.
Figure 102.
ATmega8(L) Table 78. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
Table 80. Boot Reset Fuse(1) BOOTRST Note: Store Program Memory Control Register – SPMCR Reset Address 1 Reset Vector = Application Reset (address 0x0000) 0 Reset Vector = Boot Loader Reset (see Table 82 on page 217) 1. “1” means unprogrammed, “0” means programmed The Store Program memory Control Register contains the control bits needed to control the Boot Loader operations.
ATmega8(L) page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire page write operation if the NRWW section is addressed. • Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes page erase.
Figure 103. Addressing the Flash during SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PAGE ADDRESS WITHIN THE FLASH PCWORD WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Notes: Self-Programming the Flash 1. The different variables used in the figure are listed in Table 84 on page 218. 2. PCPAGE and PCWORD are listed in Table 93 on page 224.
ATmega8(L) Assembly Code Example for a Boot Loader” on page 216 for an assembly code example. Performing Page Erase by SPM Filling the Temporary Buffer (Page Loading) To execute page erase, set up the address in the Z-pointer, write “X0000011” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation.
Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock Bits, write the desired data to R0, write “X0001001” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The only accessible Lock Bits are the Boot Lock Bits that may prevent the Application and Boot Loader section from any software update by the MCU.
ATmega8(L) Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during self-programming (page erase and page write).
ATmega8(L) sbiw loophi:looplo, 1 brne Rdloop ;use subi for PAGESIZEB<=256 ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
Note: The different BOOTSZ Fuse configurations are shown in Figure 102. Table 83. Read-While-Write Limit Section Pages Address Read-While-Write section (RWW) 96 0x000 - 0xBFF No Read-While-Write section (NRWW) 32 0xC00 - 0xFFF For details about these two section, see “NRWW – No Read-While-Write Section” on page 207 and “RWW – Read-While-Write Section” on page 207 Table 84.
ATmega8(L) Memory Programming Program And Data Memory Lock Bits The ATmega8 provides six Lock Bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 86. The Lock Bits can only be erased to “1” with the Chip Erase command. Table 85.
Table 86. Lock Bit Protection Modes(2) (Continued) Memory Lock Bits 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.
ATmega8(L) Table 88. Fuse Low Byte Fuse Low Byte Bit No.
Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock Bits, and Fuse Bits in the ATmega8. Pulses are assumed to be at least 250 ns unless otherwise noted. Signal Names In this section, some pins of the ATmega8 are referenced by signal names describing their functionality during parallel programming, see Figure 104 and Table 89.
ATmega8(L) Table 89. Pin Name Mapping (Continued) Signal Name in Programming Mode Pin Name I/O PAGEL PD7 I Program memory and EEPROM Data Page Load BS2 PC2 I Byte Select 2 (“0” selects Low byte, “1” selects 2’nd High byte) {PC[1:0]: PB[5:0]} I/O DATA Function Bi-directional Data bus (Output when OE is low) Table 90. Pin Values used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 91.
Table 93. No. of Words in a Page and no. of Pages in the Flash Flash Size 4K words (8K bytes) Page Size PCWORD No. of Pages PCPAGE PCMSB 32 words PC[4:0] 128 PC[11:5] 11 Table 94. No. of Words in a Page and no. of Pages in the EEPROM EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8 Parallel Programming Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5 - 5.
ATmega8(L) Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock Bits. The Lock Bits are not reset until the Program memory has been completely erased. The Fuse Bits are not changed. A Chip Erase must be performed before the Flash and/or the EEPROM are reprogrammed. Note: 1. The EEPRPOM memory is preserved during chip erase if the EESAVE Fuse is programmed. Load Command “Chip Erase” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3.
While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 105 on page 226. Note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address Low byte are used to address the page when performing a page write. G. Load Address High byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “1”. This selects high address. 3.
ATmega8(L) Figure 106. Programming the Flash Waveforms(1) F A DATA 0x10 B ADDR. LOW C DATA LOW D E B C D E DATA HIGH XX ADDR. LOW DATA LOW DATA HIGH XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: Programming the EEPROM 1. “XX” is don’t care. The letters refer to the programming description above. The EEPROM is organized in pages, see Table 94 on page 224. When programming the EEPROM, the program data is latched into a page buffer.
Figure 107. Programming the EEPROM Waveforms K A DATA 0x11 G ADDR. HIGH B C ADDR. LOW DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 225 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. G: Load Address High byte (0x00 - 0xFF). 3. B: Load Address Low byte (0x00 - 0xFF). 4.
ATmega8(L) Programming the Fuse High Bits The algorithm for programming the Fuse high bits is as follows (refer to “Programming the Flash” on page 225 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”. This selects low data byte.
Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 225 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low byte (0x00 - 0x02). 3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA. 4. Set OE to “1”.
ATmega8(L) Figure 111. Parallel Programming Timing, Reading Sequence (within the same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE tOHDZ DATA ADDR0 (Low Byte) ADDR1 (Low Byte) DATA (High Byte) DATA (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 109 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 95.
Table 95. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter tBVDV BS1 Valid to DATA valid tOLDV tOHDZ Notes: Serial Downloading Serial Programming Pin Mapping Min Max Units 250 ns OE Low to DATA Valid 250 ns OE High to DATA Tri-stated 250 ns 0 Typ 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock Bits commands. 2. tWLRH_CE is valid for the Chip Erase command.
ATmega8(L) Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz Serial Programming Algorithm When writing serial data to the ATmega8, data is clocked on the rising edge of SCK. When reading data from the ATmega8, data is clocked on the falling edge of SCK. See Figure 113 for timing details.
Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling.
ATmega8(L) Table 98. Serial Programming Instruction Set Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte4 Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. Read Program Memory 0010 H000 0000 aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b.
SPI Serial Programming Characteristics 236 For characteristics of the SPI module, see “SPI Timing Characteristics” on page 241.
ATmega8(L) Electrical Characteristics Note: Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. Absolute Maximum Ratings* Operating Temperature ................................. -55°C to +125°C *NOTICE: Storage Temperature ....................................
TA = -40°C to 85°C, VCC = 2.7V to 5.
ATmega8(L) External Clock Drive Waveforms Figure 114. External Clock Drive Waveforms V IH1 V IL1 External Clock Drive Table 99. External Clock Drive VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Symbol Parameter Min Max Min Max Units 1/tCLCL Oscillator Frequency 0 8 0 16 MHz tCLCL Clock Period 125 62.5 ns tCHCX High Time 50 25 ns tCLCX Low Time 50 25 ns tCLCH Rise Time 1.6 0.5 µs tCHCL Fall Time 1.6 0.
Two-wire Serial Interface Characteristics Table 101 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 115. Table 101. Two-wire Serial Bus Requirements Symbol Parameter VIL Min Max Units Input Low-voltage -0.5 0.3 VCC V VIH Input High-voltage 0.7 VCC VCC + 0.5 V Vhys(1) Hysteresis of Schmitt Trigger Inputs 0.
ATmega8(L) 5. This requirement applies to all ATmega8 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. 6. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz. 7.
Figure 116. SPI interface timing requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 7 MOSI (Data Output) MSB 8 ... LSB Figure 117. SPI interface timing requirements (Slave Mode) 18 SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 242 MSB 17 ...
ATmega8(L) ADC Characteristics Table 103. ADC Characteristics Symbol Max(1) Resolution Single Ended Conversion 10 Bits Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz 1.75 LSB Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1 MHz 3 LSB Integral Non-linearity (INL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz 0.75 LSB Differential Non-linearity (DNL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz 0.
ATmega8 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with Railto-Rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
ATmega8(L) Figure 119. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 30 5.5V 25 5.0V 4.5V ICC (mA) 20 15 10 3.3V 3.0V 5 2.7V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 120. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 18 16 -40°C 25°C 85°C 14 ICC (mA) 12 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
Figure 121. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 12 10 -40°C 25°C 85°C ICC (mA) 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 122. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 6 25°C -40°C 85°C 5 ICC (mA) 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 123. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 3.5 3 85°C 25°C ICC (mA) 2.5 -40°C 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 124. Active Supply Current vs. VCC (32 kHz External Oscillator) ACTIVE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL OSCILLATOR 120 100 25°C ICC (uA) 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
Idle Supply Current Figure 125. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 0.7 5.5V ICC (mA) 0.6 5.0V 0.5 4.5V 0.4 4.0V 3.3V 3.0V 2.7V 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 126. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz ICC (mA) 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 3.0V 2 2.
ATmega8(L) Figure 127. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 8 -40°C 25°C 85°C 7 6 ICC (mA) 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 128. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 4 -40°C 25°C 85°C 3.5 3 ICC (mA) 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 129. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 1.8 -40°C 85°C 25°C 1.6 1.4 ICC (mA) 1.2 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 130. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 1 85°C 25°C -40°C 0.9 0.8 ICC (mA) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 131. Idle Supply Current vs. VCC (32 kHz External Oscillator) IDLE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL OSCILLATOR 40 35 25°C 30 ICC (uA) 25 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-down Supply Current Figure 132. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 2.5 85°C 2 1.5 ICC (uA) -40°C 25°C 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 133. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. V CC WATCHDOG TIMER ENABLED 80 85°C 25°C -40°C 70 60 ICC (uA) 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-save Supply Current Figure 134. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) POWER-SAVE SUPPLY CURRENT vs. V CC WATCHDOG TIMER DISABLED 25 20 25°C ICC (uA) 15 10 5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Standby Supply Current Figure 135. Standby Supply Current vs. VCC (455 kHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC 455 kHz RESONATOR, WATCHDOG TIMER DISABLED 80 70 60 ICC (uA) 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 136. Standby Supply Current vs. V CC (1 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC 1 MHz RESONATOR, WATCHDOG TIMER DISABLED 70 60 ICC (uA) 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.
Figure 137. Standby Supply Current vs. V CC (2 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC 2 MHz RESONATOR, WATCHDOG TIMER DISABLED 90 80 70 ICC (uA) 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 138. Standby Supply Current vs. VCC (2 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC 2 MHz XTAL, WATCHDOG TIMER DISABLED 90 80 70 ICC (uA) 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 139. Standby Supply Current vs. V CC (4 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC 4 MHz RESONATOR, WATCHDOG TIMER DISABLED 140 120 ICC (uA) 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 140. Standby Supply Current vs. VCC (4 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC 4 MHz XTAL, WATCHDOG TIMER DISABLED 140 120 ICC (uA) 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
Figure 141. Standby Supply Current vs. V CC (6 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC 6 MHz RESONATOR, WATCHDOG TIMER DISABLED 160 140 120 ICC (uA) 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 142. Standby Supply Current vs. VCC (6 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC 6 MHz XTAL, WATCHDOG TIMER DISABLED 200 180 160 140 ICC (uA) 120 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Pin Pull-up Figure 143. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 160 85°C 140 25°C 120 -40°C IIO (uA) 100 80 60 40 20 0 0 1 2 3 4 5 6 VOP (V) Figure 144. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 90 80 85°C 25°C 70 -40°C IIO (uA) 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
Figure 145. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5V 100 - 40 °C 25°C 80 IRESET (uA) 85°C 60 40 20 0 0 1 2 VRESET (V) Figure 146. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 45 -40°C 40 25°C 35 85°C IRESET (uA) 30 25 20 15 10 5 0 0 0.5 1 1.5 2 2.
ATmega8(L) Pin Driver Strength Figure 147. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 80 -40°C 70 25°C 60 85°C IOH (mA) 50 40 30 20 10 0 VOH (V) Figure 148. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 30 -40°C 25 25°C 85°C IOH (mA) 20 15 10 5 0 0 0.5 1 1.5 2 2.
Figure 149. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 90 80 -40°C 70 25°C IOL (mA) 60 85°C 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 150. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 35 -40°C 30 25°C 25 IOL (mA) 85°C 20 15 10 5 0 0 0.5 1 1.5 2 2.
ATmega8(L) Figure 151. Reset Pin as I/O – Pin Source Current vs. Output Voltage (VCC = 5V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 4 3.5 -40°C 3 Current (mA) 25°C 2.5 85°C 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 VOH (V) Figure 152. Reset Pin as I/O – Pin Source Current vs. Output Voltage (VCC = 2.7V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 5 4.5 25°C -40°C 4 Current (mA) 3.5 3 2.5 85°C 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.
Figure 153. Reset Pin as I/O – Pin Sink Current vs. Output Voltage (VCC = 5V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 14 -40°C 12 25°C Current (mA) 10 85°C 8 6 4 2 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 154. Reset Pin as I/O – Pin Sink Current vs. Output Voltage (VCC = 2.7V) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 4.5 4 -40°C 3.5 25°C Current (mA) 3 85°C 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.
ATmega8(L) Pin Thresholds and Hysteresis Figure 155. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2.5 -40°C 85°C 25°C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 156. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2 -40°C 25°C 85°C Threshold (V) 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 157. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.7 Input Hysteresis (V) 0.6 85°C -40°C 25°C 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 158. Reset Pin as I/O – Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 4 -40°C 85°C 25°C 3.5 Threshold (V) 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 159. Reset Pin as I/O – Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 2.5 85°C 25°C -40°C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 160. Reset Pin as I/O – Pin Hysteresis vs. VCC RESET PIN AS I/O - PIN HYSTERESIS vs. VCC 2 -40°C 85°C 25°C Input Hysteresis (V) 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 161. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 2.5 -40°C 25°C 85°C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 162. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 2.5 85°C 25°C -40°C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 163. Reset Input Pin Hysteresis vs. VCC RESET INPUT PIN HYSTERESIS vs. VCC 1 Input Hysteresis (V) 0.8 -40°C 0.6 25°C 0.4 85°C 0.2 0 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Bod Thresholds and Analog Comparator Offset Figure 164. BOD Thresholds vs. Temperature (BOD Level is 4.0V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.0V 4.3 4.2 Rising VCC Threshold (V) 4.1 4 Falling VCC 3.9 3.8 3.
Figure 165. BOD Thresholds vs. Temperature (BOD Level is 2.7v) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 2.8 2.7 Threshold (V) Rising VCC 2.6 Falling VCC 2.5 2.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (˚C) Figure 166. Bandgap Voltage vs. VCC BANDGAP VOLTAGE vs. VCC Bandgap Voltage (V) 1.315 1.31 -40° 1.305 85° 25° 1.3 1.295 1.29 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 167. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 5V 0.003 Comparator Offset Voltage (V) 0.002 0.001 0 -0.001 85° -0.002 -0.003 25°C -0.004 -0.005 -40° -0.006 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Figure 168. Analog Comparator Offset Voltage vs. Common Mode Voltage (V CC = 2.7V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 2.7V 0.
Internal Oscillator Speed Figure 169. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 1260 -40°C 25°C 1240 85°C 1220 FRC (kHz) 1200 1180 1160 1140 1120 1100 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 170. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.5 5.5V 8.3 8.1 4.0V FRC (MHz) 7.9 7.7 7.5 2.7V 7.3 7.1 6.9 6.7 6.
ATmega8(L) Figure 171. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC 8.5 -40°C 8.3 25°C 8.1 FRC (MHz) 7.9 85°C 7.7 7.5 7.3 7.1 6.9 6.7 6.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 172. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs.
Figure 173. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 4.2 5.5V 4.1 4.0V FRC (MHz) 4 3.9 2.7V 3.8 3.7 3.6 3.5 -60 -40 -20 0 20 40 60 80 100 Temperature (˚C) Figure 174. Calibrated 4 MHz RC Oscillator Frequency vs. VCC CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. VCC 4.2 -40°C 4.1 25°C 4 FRC (MHz) 85°C 3.9 3.8 3.7 3.6 3.5 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 175. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 8 7 FRC (MHz) 6 5 4 3 2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Figure 176. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 2.1 5.5V 2.05 4.0V FRC (MHz) 2 1.95 2.7V 1.9 1.85 1.
Figure 177. Calibrated 2 MHz RC Oscillator Frequency vs. VCC CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. VCC 2.2 2.1 -40°C FRC (MHz) 25°C 2 85°C 1.9 1.8 1.7 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 178. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 3.8 3.3 FRC (MHz) 2.8 2.3 1.8 1.3 0.
ATmega8(L) Figure 179. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1.04 5.5V 1.02 4.0V FRC (MHz) 1 0.98 2.7V 0.96 0.94 0.92 0.9 -60 -40 -20 0 20 40 60 80 100 Temperature (˚C) Figure 180. Calibrated 1 MHz RC Oscillator Frequency vs. VCC CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. VCC 1.1 1.05 FRC (MHz) -40°C 25°C 1 85°C 0.95 0.9 2.5 3 3.5 4 4.5 5 5.
Figure 181. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 1.9 1.7 FRC (MHz) 1.5 1.3 1.1 0.9 0.7 0.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Current Consumption of Peripheral Units Figure 182. Brown-out Detector Current vs. VCC BROWN-OUT DETECTOR CURRENT vs. VCC 30 25 -40°C 25°C 85°C ICC (uA) 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 183. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs. VCC AREF = AVCC 450 400 25°C -40°C 350 85°C ICC (uA) 300 250 200 150 100 50 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 184. AREF External Reference Current vs. VCC AREF EXTERNAL REFERENCE CURRENT vs. VCC 250 85°C 200 25°C -40°C ICC (uA) 150 100 50 0 2.5 3 3.5 4 4.5 5 5.
Figure 185. 32 kHz TOSC Current vs. VCC (Watchdog Timer Disabled) 32 kHz TOSC CURRENT vs. V CC WATCHDOG TIMER DISABLED 25 20 25°C ICC (uA) 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 186. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs. V CC 80 70 85°C 60 -40°C 25°C ICC (uA) 50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.
ATmega8(L) Figure 187. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 100 85°C 90 25°C 80 -40°C 70 ICC (uA) 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 188. Programming Current vs. VCC PROGRAMMING CURRENT vs. VCC 7 -40°C 6 25°C ICC (mA) 5 85°C 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
Current Consumption in Reset and Reset Pulsewidth Figure 189. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. VCC 0.1 - 1 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP 4 5.5V 3.5 5.0V 3 4.5V ICC (mA) 2.5 4.0V 2 3.3V 3.0V 2.7V 1.5 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 190. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs.
ATmega8(L) Figure 191. Reset Pulse Width vs. VCC RESET PULSE WIDTH vs. VCC 1400 1200 Pulsewidth (ns) 1000 800 600 85°C 25°C 400 -40°C 200 0 2.5 3 3.5 4 4.5 5 5.
Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x3F (0x5F) SREG I T H S V N Z C Page 9 0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 11 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11 0x3C (0x5C) Reserved 0x3B (0x5B) GICR INT1 INT0 – – – – IVSEL IVCE 47, 65 0x3A (0x5A) GIFR INTF1 INTF0 – – – – – – 66 0x39 (0x59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 70, 100, 120 0x38 (0x58) TIFR OCF2 TO
ATmega8(L) Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x01 (0x21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 170 0x00 (0x20) TWBR Notes: Two-wire Serial Interface Bit Rate Register 168 1. Refer to the USART description for details on how to access UBRRH and UCSRC. 2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 3.
Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers
ATmega8(L) Instruction Set Summary (Continued) BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd ← Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc.
Instruction Set Summary (Continued) CLT Clear T in SREG T←0 T 1 SEH Set Half Carry Flag in SREG H←1 H 1 CLH Clear Half Carry Flag in SREG H←0 H 1 MCU CONTROL INSTRUCTIONS NOP SLEEP WDR No Operation Sleep Watchdog Reset (see specific descr. for Sleep function) (see specific descr.
ATmega8(L) Ordering Information Speed (MHz) Power Supply Ordering Code Package Operation Range 8 2.7 - 5.5 ATmega8L-8AC ATmega8L-8PC ATmega8L-8MC 32A 28P3 32M1-A Commercial (0°C to 70°C) ATmega8L-8AI ATmega8L-8PI ATmega8L-8MI 32A 28P3 32M1-A Industrial (-40°C to 85°C) ATmega8-16AC ATmega8-16PC ATmega8-16MC 32A 28P3 32M1-A Commercial (0°C to 70°C) ATmega8-16AI ATmega8-16PI ATmega8-16MI 32A 28P3 32M1-A Industrial (-40°C to 85°C) 16 Note: 4.5 - 5.
Packaging Information 32A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.
ATmega8(L) 28P3 D PIN 1 E1 A SEATING PLANE L B2 B1 A1 B (4 PLACES) 0º ~ 15º REF e E C COMMON DIMENSIONS (Unit of Measure = mm) eB Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). MIN NOM MAX – – 4.5724 A1 0.508 – – D 34.544 – 34.798 E 7.620 – 8.255 E1 7.112 – 7.493 B 0.381 – 0.533 B1 1.143 – 1.397 B2 0.762 – 1.143 L 3.175 – 3.429 C 0.203 – 0.356 eB – – 10.
32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A 0.08 C P COMMON DIMENSIONS (Unit of Measure = mm) D2 Pin 1 ID 1 2 3 P E2 SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 b 0.20 REF 0.18 D L D2 3.25 4.75BSC 2.95 e Notes: 1. JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 3.10 5.00 BSC E1 E2 0.30 4.75 BSC 2.95 E BOTTOM VIEW 0.23 5.00 BSC D1 e b NOTE 3.10 3.25 0.50 BSC L 0.30 0.40 0.50 P – – 0 – – 0.
ATmega8(L) Erratas The revision letter in this section refers to the revision of the ATmega8 device. ATmega8 Rev. D, E, F, and G • CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32 KHz Oscillator is Used to Clock the Asynchronous Timer/Counter2 1.
Datasheet Change Log for ATmega8 This document contains a log on the changes made to the datasheet for ATmega8. Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03 All page numbers refers to this document. Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03 All page numbers refers to this document. 1. Updated “Calibrated Internal RC Oscillator” on page 28. 1. Removed “Preliminary” and TBDs from the datasheet. 2. Renamed ICP to ICP1 in the datasheet. 3.
ATmega8(L) 1. Improved the description of “Asynchronous Timer Clock – clkASY” on page 24. 2. Removed reference to the “Multipurpose Oscillator” application note and the “32 kHz Crystal Oscillator” application note, which do not exist. 3. Corrected OCn waveforms in Figure 38 on page 88. 4. Various minor Timer 1 corrections. 5. Various minor TWI corrections. 6. Added note under “Filling the Temporary Buffer (Page Loading)” on page 213 about writing to the EEPROM during an SPM Page load. 7.
Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02 All page numbers refers to this document. Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02 All page numbers refers to this document. 1 Updated Table 103, “ADC Characteristics,” on page 243. 1 Changes in “Digital Input Enable and Sleep Modes” on page 53. 2 Addition of OCS2 in “MOSI/OC2 – Port B, Bit 3” on page 57.
ATmega8(L) Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02 All page numbers refers to this document. 1 Updated TWI Chapter. More details regarding use of the TWI Power-down operation and using the TWI as Master with low TWBRR values are added into the datasheet. Added the note at the end of the “Bit Rate Generator Unit” on page 167. Added the description at the end of “Address Match Unit” on page 167. 2 Updated Description of OSCCAL Calibration Byte.
ATmega8(L) 2486M–AVR–12/03
ATmega8(L) Table of Contents Features................................................................................................ 1 Pin Configurations............................................................................... 2 Overview ............................................................................................... 3 Block Diagram ...................................................................................................... 3 Disclaimer ......................................
System Control and Reset ................................................................ 35 Internal Voltage Reference ................................................................................. 40 Watchdog Timer ................................................................................................. 41 Timed Sequences for Changing the Configuration of the Watchdog Timer ....... 43 Interrupts ............................................................................................
ATmega8(L) 8-bit Timer/Counter Register Description ......................................................... 115 Asynchronous Operation of the Timer/Counter ................................................ 117 Timer/Counter Prescaler................................................................................... 121 Serial Peripheral Interface – SPI..................................................... 122 SS Pin Functionality..............................................................................
Boot Loader Support – Read-While-Write Self-Programming ..... 206 Boot Loader Features ....................................................................................... Application and Boot Loader Flash Sections .................................................... Read-While-Write and No Read-While-Write Flash Sections........................... Boot Loader Lock Bits....................................................................................... Entering the Boot Loader Program ................
ATmega8(L) Datasheet Change Log for ATmega8............................................. 292 Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03.................................... Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03.................................... Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03.................................... Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03 ..................................... Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02 .......................
6 ATmega8(L) 2486M–AVR–12/03
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