Datasheet

241
ATmega8(L)
2486M–AVR–12/03
5. This requirement applies to all ATmega8 Two-wire Serial Interface operation. Other
devices connected to the Two-wire Serial Bus need only obey the general f
SCL
requirement.
6. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/f
SCL
- 2/f
CK
), thus f
CK
must be greater than 6 MHz for the low time requirement to be
strictly met at f
SCL
= 100 kHz.
7. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/f
SCL
- 2/f
CK
), thus the low time requirement will not be strictly met for f
SCL
> 308 kHz when
f
CK
= 8 MHz. Still, ATmega8 devices connected to the bus may communicate at full
speed (400 kHz) with other ATmega8 devices, as well as any other device with a
proper t
LOW
acceptance margin.
Figure 115. Two-wire Serial Bus Timing
SPI Timing
Characteristics
See Figure 116 and Figure 117 for details.
Note: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2t
CLCL
for f
CK
< 12 MHz
- 3t
CLCL
for f
CK
> 12 MHz
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
SDA
t
r
Table 102. SPI Timing Parameters
Description Mode Min Typ Max
1 SCK period Master See Table 50
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 • t
SCK
7 SCK to out Master 10
8 SCK to out high Master 10
9 SS low to out Slave 15
10 SCK period Slave 4 • t
ck
11 SCK high/low
(1)
Slave 2 • t
ck
12 Rise/Fall time Slave 1.6
13 Setup Slave 10
14 Hold Slave 10
15 SCK to out Slave 15
16 SCK to SS high Slave 20
17 SS high to tri-state Slave 10
18 SS low to SCK Salve 2 • t
ck