Datasheet

v
8011K–AVR–09/08
ATmega164P/324P/644P
20.6 Using the TWI .....................................................................................................216
20.7 Transmission Modes ..........................................................................................219
20.8 Multi-master Systems and Arbitration .................................................................232
20.9 Register Description ...........................................................................................233
21 AC - Analog Comparator ..................................................................... 238
21.1 Overview ............................................................................................................238
21.2 Analog Comparator Multiplexed Input ................................................................238
21.3 Register Description ...........................................................................................239
22 ADC - Analog-to-digital Converter ..................................................... 241
22.1 Features .............................................................................................................241
22.2 Overview ............................................................................................................241
22.3 Operation ............................................................................................................242
22.4 Starting a Conversion .........................................................................................243
22.5 Prescaling and Conversion Timing .....................................................................244
22.6 Changing Channel or Reference Selection ........................................................247
22.7 ADC Noise Canceler ..........................................................................................249
22.8 ADC Conversion Result .....................................................................................254
22.9 Register Description ...........................................................................................256
23 JTAG Interface and On-chip Debug System ..................................... 261
23.1 Features .............................................................................................................261
23.2 Overview ............................................................................................................261
23.3 TAP – Test Access Port .....................................................................................261
23.4 TAP Controller ....................................................................................................263
23.5 Using the Boundary-scan Chain .........................................................................264
23.6 Using the On-chip Debug System ......................................................................264
23.7 On-chip Debug Specific JTAG Instructions ........................................................265
23.8 Using the JTAG Programming Capabilities ........................................................265
23.9 Bibliography ........................................................................................................266
23.10 Register Description .........................................................................................266
24 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 267
24.1 Features .............................................................................................................267
24.2 Overview ............................................................................................................267
24.3 Data Registers ....................................................................................................268
24.4 Boundary-scan Specific JTAG Instructions ........................................................269
24.5 Boundary-scan Chain .........................................................................................270