Datasheet

264
2467X–AVR–06/11
ATmega128
The Atmel
®
AVR
®
ADC is based on the analog circuitry shown in Figure 131 with a successive
approximation algorithm implemented in the digital logic. When used in Boundary-scan, the
problem is usually to ensure that an applied analog voltage is measured within some limits. This
can easily be done without running a successive approximation algorithm: apply the lower limit
on the digital DAC[9:0] lines, make sure the output from the comparator is low, then apply the
upper limit on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following
• The Port Pin for the ADC channel in use must be configured to be an input with pull-up
disabled to avoid signal contention.
• In normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal
low (Sample mode).
As an example, consider the task of verifying a 1.5V ±5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
CC
.
The recommended values from Table 104 are used unless other values are given in the algo-
rithm in Table 105. Only the DAC and Port Pin values of the Scan Chain are shown. The column
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Table 105. Algorithm for Using the ADC
Step Actions ADCEN DAC MUXEN HOLD PRECH
PA3.
Data
PA3 .
Control
PA3.
Pullup_
Enable
1
SAMPLE_
PRELOAD
1 0x200 0x08 1 1 0 0 0
2 EXTEST 1 0x200 0x08 0 1 0 0 0
3 1 0x200 0x08 1 1 0 0 0
4 1 0x123 0x08 1 1 0 0 0
5 1 0x123 0x08 1 0 0 0 0
6
Verify the
COMP bit
scanned
out to be 0
1 0x200 0x08 1 1 0 0 0
7 1 0x200 0x08 0 1 0 0 0
8 1 0x200 0x08 1 1 0 0 0
The lower limit is: 1024 1.5V 0,95 5V⁄⋅⋅ 291 0x123==
The upper limit is: 1024 1.5V 1.05 5V⁄⋅⋅ 323 0x143==