Datasheet

263
2467X–AVR–06/11
ATmega128
Note: Incorrect setting of the switches in Figure 131 will make signal contention and may damage the
part. There are several input choices to the S&H circuitry on the negative input of the output com-
parator in Figure 131. Make sure only one path is selected from either one ADC pin, Bandgap
reference source, or Ground.
If the ADC is not to be used during scan, the recommended input values from Table 104 should
be used. The user is recommended not to use the Differential Gain stages during scan. Switch-
Cap based gain stages require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential gain stage is there-
fore not provided.
MUXEN_7 Input Input Mux bit 7 0 0
MUXEN_6 Input Input Mux bit 6 0 0
MUXEN_5 Input Input Mux bit 5 0 0
MUXEN_4 Input Input Mux bit 4 0 0
MUXEN_3 Input Input Mux bit 3 0 0
MUXEN_2 Input Input Mux bit 2 0 0
MUXEN_1 Input Input Mux bit 1 0 0
MUXEN_0 Input Input Mux bit 0 1 1
NEGSEL_2 Input Input Mux for negative
input for differential signal,
bit 2
00
NEGSEL_1 Input Input Mux for negative
input for differential signal,
bit 1
00
NEGSEL_0 Input Input Mux for negative
input for differential signal,
bit 0
00
PASSEN Input Enable pass-gate of gain
stages.
11
PRECH Input Precharge output latch of
comparator. (Active low)
11
SCTEST Input Switch-cap TEST enable.
Output from x10 gain
stage send out to Port Pin
having ADC_4
00
ST Input Output of gain stages will
settle faster if this signal is
high first two ACLK
periods after AMPEN goes
high.
00
VCCREN Input Selects Vcc as the ACC
reference voltage.
00
Table 104. Boundary-scan Signals for the ADC (Continued)
Signal
Name
Direction
as Seen
from the
ADC Description
Recommended
Input
when not
in Use
Output Values when
Recommended Inputs
are Used, and CPU is
not Using the ADC